Cost competitiveness is a major driving force in the semiconductor industry. The processing cost of an individual die is directly proportional to its size. Advances in processing technology have shrunk the device sizes in wire-bonded chips, resulting in a smaller die core size. However, the space below wire-bond pads remains relatively underutilized because of the reliability concern that electrical loads transmitted during bonding can cause failures in the underlying devices. Recently, studies have attempted to improve the use of space below wire-bond pads. Hence, the circuits under pads (CUP) structure modified layout rules to include circuits structure under pads, was developed, and extensive qualification work is required to meet reliability standards.
The main purpose of this paper is to investigate the damage caused by the wirebonding process of CUP devices on the in-line assembly packaging manufacture. The root cause of wirebonding failures analyzed were based on the CUP structure and several wire bond parameters; such as bonding force, ultrasonic current, bonding time period, capillary type, machine, and wafer source, which were also confirmed with the DOE/JMP engineer technique. Finally, results were also used to implement the corrective action and the assembly yield of CUP Device has been improved, successfully.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0728107-121433 |
| Date | 28 July 2007 |
| Creators | Wu, Chia-Ying |
| Contributors | W. C. Hsu, H. Y. Ueng, Chih-Hsiung Liao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728107-121433 |
| Rights | not_available, Copyright information available at source archive |
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