The objective of this thesis is to design a high speed digital FIR filter. The inputs of the
system come from a Delta-Sigma modulator. This FIR filter takes 1024 inputs,
multiplies them with their coefficients and adds the results. The main design task is to
take the input data, which are unweighted single-bit binary numbers at 156MHz,
multiply each bit with the corresponding coefficient and add them to get a weighted
multi-bit output at 20MHz. / Graduation date: 1997
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/34326 |
| Date | 02 December 1996 |
| Creators | Zhou, Bo |
| Contributors | Lu, Shih-Lien |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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