As semiconductor technology scales down, process variations become increasingly difficult to control. To cope with this, more and more conservative delay and clock frequency estimations are used during design, which result in overly large and leaky circuits. Also, the system runs at a speed slower than that possible because a fixed clock determined by the worst-case analysis of the circuit is used. On top of process variations, voltage and temperature variations also push the designer towards even more conservative delay estimations. On the other hand, asynchronous design style has potential advantages over synchronous design including resilience to process variations, lower power consumption and higher performance. Unfortunately, these advantages are usually hindered by the significant design effort required to implement useful asynchronous circuits and also by the overhead of asynchronous control logic. Borrowing from asynchronous techniques, a new methodology is proposed to design synchronous circuits that have some of the advantages of asynchronous circuits. Asynchronous logic is used to generate the clock of a synchronous system. The resulting system automatically tunes itself to deliver the best-possible performance under the prevailing process-voltage-temperature (PVT) conditions. This methodology may be used to reduce the leakage power significantly in deep nanometer technologies. It also helps in handling process variations. The results from a 32-bit processor implemented in 90nm technology shows 10X leakage reduction compared to the traditional synchronous design. The proposed technique is expanded to adjust the speed of a pipeline according to the current operations flowing in the pipeline as well as the current PVT conditions. The results from a 32-bit processor in 90nm technology demonstrate a 2X speed improvement compared to the conventional synchronous design. The proposed techniques only use synchronous design tools and are compatible with design flows that are currently in use.

As semiconductor technology scales down, process variations become increasingly difficult to control. To cope with this, more and more conservative delay and clock frequency estimations are used during design, which result in overly large and leaky circuits. Also, the system runs at a speed slower than that possible because a fixed clock determined by the worst-case analysis of the circuit is used. On top of process variations, voltage and temperature variations also push the designer towards even more conservative delay estimations. On the other hand, asynchronous design style has potential advantages over synchronous design including resilience to process variations, lower power consumption and higher performance. Unfortunately, these advantages are usually hindered by the significant design effort required to implement useful asynchronous circuits and also by the overhead of asynchronous control logic. Borrowing from asynchronous techniques, a new methodology is proposed to design synchronous circuits that have some of the advantages of asynchronous circuits. Asynchronous logic is used to generate the clock of a synchronous system. The resulting system automatically tunes itself to deliver the best-possible performance under the prevailing process-voltage-temperature (PVT) conditions. This methodology may be used to reduce the leakage power significantly in deep nanometer technologies. It also helps in handling process variations. The results from a 32-bit processor implemented in 90nm technology shows 10X leakage reduction compared to the traditional synchronous design. The proposed technique is expanded to adjust the speed of a pipeline according to the current operations flowing in the pipeline as well as the current PVT conditions. The results from a 32-bit processor in 90nm technology demonstrate a 2X speed improvement compared to the conventional synchronous design. The proposed techniques only use synchronous design tools and are compatible with design flows that are currently in use.

The objective of this thesis is to design a high speed digital FIR filter. The inputs of the system come from a Delta-Sigma modulator. This FIR filter takes 1024 inputs, multiplies them with their coefficients and adds the results. The main design task is to take the input data, which are unweighted single-bit binary numbers at 156MHz, multiply each bit with the corresponding coefficient and add them to get a weighted multi-bit output at 20MHz. / Graduation date: 1997

Due to advances in high-density low-cost VLSI and communication technology, digital filtering and signal processing are being widely used for real-time signal processing applications. Given the filter specification, choosing the best filter structure for a given application is not a trivial task. The choice of a particular filter structure depends on many factors such as sensitivity to finite word-length quantization effects, hardware complexity and power consumption. The objective of this thesis is to examine digital IIR (Infinite Impulse Response) filter structures for the VLSI implementation of narrow-band sharp-transition filters. This thesis examines several different digital IIR filter structures; namely cascade form IIR filter, five different digital lattice filters and lattice wave digital filter structures. For fixed-point implementation, the sensitivity, round-off noise properties and the scaling of these filter structures are described and analyzed. These filter structures are compared with respect to the architectural complexity, the sensitivity to coefficient quantization, the round-off noise due to product quantization and the signal dynamic range. Fixed-point implementation simulations using two's-complement arithmetic are carried out for a number of narrow-band sharp-transition digital low-pass filters. / Graduation date: 1995

Thesis (M.S.)--University of Wisconsin--Madison, 1970. / eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references.

Submitted by Automa??o e Estat?stica (sst@bczm.ufrn.br) on 2017-03-23T16:42:09Z No. of bitstreams: 1 MadsonEulerTavaresPereira_DISSERT.pdf: 17433029 bytes, checksum: 25b2ffcc0d75343e17d9515d89ee6bea (MD5) / Approved for entry into archive by Monica Paiva (monicalpaiva@hotmail.com) on 2017-03-23T16:48:26Z (GMT) No. of bitstreams: 1 MadsonEulerTavaresPereira_DISSERT.pdf: 17433029 bytes, checksum: 25b2ffcc0d75343e17d9515d89ee6bea (MD5) / Made available in DSpace on 2017-03-23T16:48:26Z (GMT). No. of bitstreams: 1 MadsonEulerTavaresPereira_DISSERT.pdf: 17433029 bytes, checksum: 25b2ffcc0d75343e17d9515d89ee6bea (MD5) Previous issue date: 2014-06-26 / Localizada no contexto de uma sociedade tomada pela cibercultura, esta influenciando diretamente as rela??es entre literatura, ilustra??es e novos suportes digitais de leitura, a presente disserta??o se prop?e a pensar as possibilidades do design de comunica??o no universo dos ebooks criados para tablets. Posto isto, o objetivo geral ? descrever e analisar as 26 ilustra??es din?micas interativas digitais da edi??o/vers?o gratuita de ?Alice no Pa?s das Maravilhas?, batizada de ?Alice for the Ipad? pela empresa de produtos eletr?nicos Apple. Optou-se por lan?ar m?o de uma pesquisa qualitativa, multimodal, tendo como fio condutor uma an?lise descritiva dos objetos supracitados,amparada por referenciais te?ricos e cr?ticos constantes na bibliografia do presente estudo. Almeja-se que esta abordagem em espec?fico, possibilite novos di?logos e contribua com as pesquisassobre comunica??o e produ??o de sentido no campo das ilustra??es vinculadas ?s novas tecnologias. / Localizada no contexto de uma sociedade tomada pela cibercultura, esta influenciando diretamente as rela??es entre literatura, ilustra??es e novos suportes digitais de leitura, a presente disserta??o se prop?e a pensar as possibilidades do design de comunica??o no universo dos ebooks criados para tablets. Posto isto, o objetivo geral ? descrever e analisar as 26 ilustra??es din?micas interativas digitais da edi??o/vers?o gratuita de ?Alice no Pa?s das Maravilhas?, batizada de ?Alice for the Ipad? pela empresa de produtos eletr?nicos Apple. Optou-se por lan?ar m?o de uma pesquisa qualitativa, multimodal, tendo como fio condutor uma an?lise descritiva dos objetos supracitados,amparada por referenciais te?ricos e cr?ticos constantes na bibliografia do presente estudo. Almeja-se que esta abordagem em espec?fico, possibilite novos di?logos e contribua com as pesquisassobre comunica??o e produ??o de sentido no campo das ilustra??es vinculadas ?s novas tecnologias.

<p> This thesis describes the development of an ultra low frequency digital analyzer from mathematical concepts and error characteristics set out in a publication^2 co-authored by the supervisor. The development is carried to the actual construction of a practical, economical, operating instrument, capable of giving information leading directly to the mean square value and the approximate amplitude probability distribution for ultra low frequency waveforms, both periodic and non-periodic. The final detailed design is described and justified, and the error characteristics derived in the above mentioned publication are interpreted for the design. No further development of principles or error characteristics is undertaken.</p> / Thesis / Master of Engineering (MEngr)

How form translates as it moves between the physical and the digital has caught my interest. I collect data through different types of 3d scanning exploring a range of technologies. In the digital realm, the information captured presents itself as a messy abstraction to the original where some information is added while other is lost. Developing the material, I adopt complex content aware auto fill algorithms - a strategy that becomes essential for the project.  In my installation visitors can explore thresholds between the real and the virtual. My firm belief is that the traces from the physical and digital wear and tear add value in that they unpack my process, birthing something strange while familiar. / Hur form översätts när den rör sig mellan det fysiska och det digitala har fångat mitt intresse. Jag samlar in data genom olika typer av 3d-skanning och utforskar en rad olika tekniker. I det digitala rummet redovisas den dokumenterade datan som en rörig abstraktion till sitt original, där viss information adderas medan annan förloras. Jag antar i min designprocess komplexa content aware auto fill-algoritmer - en strategi som blir central för projektet. I min installation bjuds besökare att utforska möten mellan det verkliga och det virtuella. Det är min övertygelse att spåren från det fysiska och det digitala slitaget adderar mervärden genom att de packar upp min process samtidigt som något märkligt men bekant materialiseras.

Outcomes of innovative designing are frequently described as enabling us in achieving more desirable futures. How can we design and innovate so as to enable future processes of design and innovation? To investigate this question, this thesis probes the conditions, possibilities and limitations of toolmaking for novelty and knowledge generation, or in other words, it examines designing for designing. The focus of this thesis is on the development of digital design tools that support the reconciliation of conflicting criteria centred on architectural geometry. Of particular interest are the roles of methodological approaches and of biological analogies as guides in toolmaking for design, as well as the possibility of generalising design tools beyond the contexts from which they originate. The presented investigation consists of an applied toolmaking study and a subsequent reflective analysis using second- order cybernetics as a theoretical framework. Observations made during the toolmaking study suggest that biological analogies can, in informal ways, inspire designing, including the designing of design tools. Design tools seem to enable the generation of novelty and knowledge beyond the contexts in and for which they are developed only if their users apply them in ways unanticipated by the toolmaker. Abstract The reflective analysis offers theoretical explanations for these observations based on aspects of second-order cybernetics. These aspects include the modelling of designing as a conversation, different relationships between observers (such as designers) and systems (such as designers engaged in their projects), the distinction between coded and uncoded knowledge, as well as processes underlying the production and the restriction of meaning. Initially aimed at the development of generally applicable, prescriptive digital tools for designing, the presented work results in a personal descriptive model of novelty and knowledge generation in science and design. This shift indicates a perspective change from a positivist to a relativist outlook on designing, which was accomplished over the course of the study. Investigating theory and practice of designing and of science, this study establishes an epistemological model of designing that accommodates and extends a number of theoretical concepts others have previously proposed. According to this model, both design and science generate and encode new knowledge through conversational processes, in which open-minded perception appears to be of greater innovative power than efforts to exercise control. The presented work substantiates and exemplifies radical constructivist theory of knowledge and novelty production, establishes correspondences between systems theory and design research theory and implies that mainstream scientific theories and practices are insufficient to account for and to guide innovation. Keywords (separated by commas) Digital design tools, geometry rationalisation, second-order cybernetics, knowledge generation

A new structure for the implementation of bit/serial adaptive IIR filter is presented. The bit level system consists of gated full adders for the arithmetic unit and data latches for the data path. This approach allows recursive operation of the IIR filter to be implemented without any global interconnections, minimal delay time, chip area and I/O pins. The coefficients of the filter can be updated serially in real time for time invariant and adaptive filtering. A fourth order bit/serial IIR filter is implemented on a 2 micron CMOS technology clocked at 55 MHz. / Graduation date: 1992