Approved for public release, distribution is unlimited / This thesis discusses VHDL modeling and simulation of a full custom Application Specific Integrated Circuit (ASIC) for a Digital Image Synthesizer (DIS). The DIS synthesizes the characteristic echo signature of a pre-selected target. It is mainly used against Inverse Synthetic Aperture Radars as an electronic counter measure. The VHDL description of the DIS architecture was exported from Tanner S-Edit, modified, and simulated in Aldec Active HDLTM. Simulation results were compared with C++ and Matlab simulation results for verification. Main subcomponents, a single Range Bin Processor (RBP), a cascade of 4 RBP s and a cascade of 16 RBP s were tested and verified. The overhead control circuitry, including Self Test Circuitry and Phase Extractor, was tested separately. Finally overall DIS was tested and verified using the control circuitry and a cascade of 4 RBP s together, representing the actual 512 RBP s. As a result of this research, the majority of the DIS was functionally tested and verified. / First Lieutenant, Turkish Army
| Identifer | oai:union.ndltd.org:nps.edu/oai:calhoun.nps.edu:10945/964 |
| Date | 06 1900 |
| Creators | Kantemir, Ozkan |
| Contributors | Fouts, Douglas J., Pace, Phillip E., Department of Electrical and Computer Engineering |
| Publisher | Monterey, California. Naval Postgraduate School |
| Source Sets | Naval Postgraduate School |
| Detected Language | English |
| Type | Thesis |
| Format | xvi, 146 p. : ill. (some col.), application/pdf |
| Rights | Copyright is reserved by the copyright owner |
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