High-speed digital to analogue converters (DAC), which are optimised for large bandwidth signal synthesis applications, are a fundamental building block and enabling technology in industrial instrumentation, military, communication and medical applications. The spurious free dynamic range (SFDR) is a key specification of high-speed DACs, as unwanted spurious signals generated by the DAC degrades the performance and effectiveness of wideband systems. The focus of this work is to enhance the SFDR performance of high-speed DACs.
As bandwidth requirements increase, meeting the desired SFDR performance is further complicated by the increase in dynamic non-linearity. The most widely used architecture in high-speed applications is the current-steering DAC fabricated on CMOS technology. The current source finite output impedance, switch distortion and clock feedthrough are the greatest contributors to dynamic non-linearity and are difficult to improve with the use of MOS devices alone. This research proposes the use of BiCMOS technology that offers high performance, using heterojunction bipolar transistors (HBT) that, when combined with MOS devices, are able to improve on the linearity of the current-steering DAC and hence improve the SFDR.
A design methodology is introduced based on BiCMOS fabrication technology to improve SFDR performance and places emphasis on the constraints of modern fabrication processes. A six-bit current-steering application-specific integrated circuit DAC is designed based on the proposed design methodology, which optimises the SFDR performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect to verify the hypothesis experimentally.
A novel current source cell is implemented that comprises HBT current switches, negative channel metal-oxide semiconductor (NMOS) cascode and NMOS current source to overcome distortion by specifically enhancing the SFDR for high-speed DACs. A switch driver and low-voltage differential signalling receiver to achieve high-speed DAC performance and their influence on the SFDR performance are designed and discussed.
The DAC is implemented using the International Business Machines Corporation (IBM) 8HP silicon germanium (SiGe) BiCMOS 130 nm technology. The DAC achieves a better than 21.96 dBc SFDR across the Nyquist band for a sampling rate of 500 MS/s with a core size of 0.1 mm2 and dissipates just 4 mW compared to other BiCMOS DACs that achieve similar SFDR performance with higher output voltages, resulting in much larger power dissipation. / Dissertation (MEng)--University of Pretoria, 2015. / Electrical, Electronic and Computer Engineering / MEng / Unrestricted
| Identifer | oai:union.ndltd.org:netd.ac.za/oai:union.ndltd.org:up/oai:repository.up.ac.za:2263/48947 |
| Date | January 2015 |
| Creators | Reddy, Reeshen |
| Contributors | Sinha, Saurabh |
| Source Sets | South African National ETD Portal |
| Language | English |
| Detected Language | English |
| Type | Dissertation |
| Rights | © 2015 University of Pretoria. All rights reserved. The copyright in this work vests in the University of Pretoria. No part of this work may be reproduced or transmitted in any form or by any means, without the prior written permission of the University of Pretoria. |
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