This thesis proposes a novel fully digital technique for the estimation and
correction of the DAC error in multi-bit delta sigma ADCs. The structure of the
DAC error is indicated through a simple model for unit-element based DACs. The
impact of the DAC error on the performance of ADC is then analyzed. Various
techniques dealing with the DAC error are described and their drawbacks are
pointed out. Based on the nature of the DAC error and the surrounding signals, a
fully digital method to estimate the error from the ADC output and remove it is
proposed. Simulation results are shown to support the effectiveness of the method.
Simulations also show that the proposed technique can work together with the
technique of adaptive compensation for quantization noise leakage in cascaded
delta sigma (MASH) ADC cases. These two techniques are the foundation for the
design of high speed, high resolution delta sigma ADCs with relaxed requirements
on the analog circuits.
To verify the proposed technique, an experimental MASH ADC was built,
including the design and fabrication of a chip of a second-order multi-bit delta
sigma ADC in a 1.6��m CMOS technology. The measured results show that the
proposed DAC correction technique is highly effective. / Graduation date: 2004
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/30720 |
| Date | 01 December 2003 |
| Creators | Wang, Xuesheng |
| Contributors | Temes, Gabor C., Moon, Un-Ku |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
Page generated in 0.0018 seconds