Demand for data communication capacity is rapidly increasing with more and more number of users and higher bandwidth services. As a result, a critical research issue is the implementation of wideband and flexible signal processing in communication and sensing applications. Although software defined radio (SDR) is a possible solution, it may not be practical due to the excessive requirements for analog-to-digital converter (ADCs) and digital filters for wideband signals. In this environment, discrete-time (DT) domain circuits are gaining attention in various architectures such as N-path filters, sampling mixers, and analog FIR/IIR/FFT filters. DT analog signal processing (DT-ASP) ahead of an ADC considerably relaxes the ADC requirements by flexible filtering, offers the potential for higher dynamic range performance, and provides robustness in the presence of digital CMOS scaling.
The primary work presented in this dissertation is the design of wideband analog finite impulse response (AFIR) filters. Analog FIR filters have been used as low pass filters for out-of-band rejection in narrow-band applications. However, this work seeks to develop AFIR filters suitable for wideband applications, extending its possible applications. To achieve these performance goals, capacitive digital to analog converters (CDACs) have been introduced for the first time as wideband analog coefficient multipliers, which has led to high linearity analog multiplication with coefficient selection at the DAC resolution. A prototype 4th order DT FIR filter has been implemented in 32nm SOI CMOS technology and has achieved low-pass, band-pass, and high-pass filter (LPF, BPF and HPF) transfer functions corresponding to the programmed coefficient sets with IIP3>11dBm linearity and less than 2 mW/tap of power consumption. The AFIR filter is also utilized to demonstrate a proof-of-concept FIR-based beamforming. The beamforming network consisting of 4 antenna element inputs followed by AFIR filters was implemented with PCB modules with the previously fabricated AFIR filter chip. Behavioral simulations are used to verify the beamforming function with given coefficient sets. Based on the developed AFIR filter modules, FIR-based beamforming was demonstrated with measurement results matching well with the simulations.
Further work presented is the design and optimization of multi-section CDAC (MS-CDAC) structures. The proposed MS-CDAC approach provides wide range of options to optimize the tradeoff between kT/C noise, linearity versus switching energy, speed and area. When the optimization approach is applied to a proof-of-concept 10-bit CDAC design, the selected MS-CDAC structure reduces total capacitance and switching energy by 97% and 98%, respectively for given linearity and noise limitations. The proposed MS-CDAC structures are applicable in both DT-ASP coefficient multiplier and SAR-ADC applications. / PHD / In communication systems, filter design is a fundamental task required to recover the signal of interest in the presence of interference. As upcoming communication systems, such as 5th generation (5G) mobile communications and future IEEE 802.11 standards (Wi-Fi), require higher speed and flexibility in signal processing due to the rapidly increasing number of users and data rates, it becomes more challenging to design such filters. In general, analog filters are useful for high-speed, digital filters features flexibility. To take advantage of both aspects, discrete-time (DT) domain filters have become a promising alternative, which can be used to implement digital signal processing functions in the analog domain.
This dissertation presents the development of DT analog finite-impulse-response (AFIR) filter design for mixed-signal processing applications. The core idea in this work is to adopt the capacitive DAC (CDAC) as a coefficient multiplier, which enables digital code coefficient multiplication as well as high-speed and high-linearity performance while consuming low power. A prototype 4th order DT FIR filter implemented in 32nm SOI CMOS process is demonstrated with measurements. Based on the developed AFIR filters, proof-of-concept FIR-based beamforming is investigated as well. For this purpose, AFIR filter modules are built on printed-circuit-boards (PCBs) and coefficients are calculated by a simplified method.
In addition, this dissertation also includes analysis and optimization of multi-section CDAC (MS-CDAC) structures. Traditional CDAC approaches have a fundamental trade-off between noise and linearity versus size, switching energy and speed. This work explores the characteristics of CDACs depending on the section segmentations and the optimal structure is selected based on the trade-off. Through comprehensive simulations and calculations, the selected structure for 10-bit MS-CDAC achieved 97% and 98% reduced total capacitance and switching energy, respectively.
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/99794 |
| Date | 27 February 2019 |
| Creators | Park, Shinwoong |
| Contributors | Electrical Engineering, Raman, Sanjay, Ha, Dong S., Davalos, Rafael V., Yi, Yang, Reed, Jeffrey H. |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Detected Language | English |
| Type | Dissertation |
| Format | ETD, application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
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