The human vestibular system is responsible for maintaining balance and orientation, and stabilizing gaze during head motion. Head motion is sensed by vestibular sensors and encoded via the firing rate of vestibular neurons. Vestibular disorders can result in dizziness, imbalance, and disequilibrium. Currently there are no therapeutic options for individuals suffering from bilateral vestibular dysfunction. A potential solution is a vestibular prosthesis (VP). This device serves to replace peripheral vestibular organs by sensing angular motion, detected by semicircular canals (SCCs), and linear head motion, detected by the otolith organs, and selectively stimulating the corresponding vestibular afferents. An ideal VP will not only mimic the patient-dependent vestibular neural dynamics, but also consume low power. In this study, three energy-efficient ways to implement the motion encoding function required in a vestibular prosthesis are presented. Both analog and digital signal processing techniques to implement the vestibular signal processing functions are investigated.

This work addresses neural and analog computation on reconfigurable mixed-signal platforms. Many engineered systems could gain tremendous benefits by emulating neural systems. For example, neural systems are incredibly power efficient and fault-tolerant. They are also capable of types of computation that we cannot yet match with conventional computers. Neuromorphic engineers typically implement neural computation using analog circuits because they are low-power and naturally model some aspects of neurobiology. One problem with analog circuits is that they are typically inflexible. To address this shortcoming, our lab has developed reconfigurable analog systems known as Field Programmable Analog Arrays (FPAAs). This dissertation consists of two main parts. The first is the implementation of neural and analog circuits on FPAAs. We first implemented an adaptive winner-take-all circuit, which could model attention in neural systems. Next, we modeled the dendrite, which is the conductive tissue that relays inputs from synapses to the neuron cell body. We also implemented a subtractive music synthesizer, perhaps providing the electronic music synthesis community with a good platform for experimentation. Finally, we conducted a number of neural learning experiments on a neuromorphic platform. The second part of this dissertation includes design aspects of new FPAAs, including configurable blocks that can be used as current-mode DACs in a digitally-enhanced FPAA, the RASP 2.9v. We also consider the design of a new neuromorphic platform containing 256 neurons and over 200,000 synapses, many with learning capability. We also created an active delay line that could be used for beamforming or FIR filter applications. In summary, this work adds to the field of reconfigurable systems by both showing how to implement circuits with them and creating new systems based on lessons learned while working with previous systems.

Le concept de Radio Logicielle propose d’intégrer en un seul circuit un émetteur / récepteur RF capable d’émettre et de recevoir n’importe quel signal RF. Cependant, ce concept doit a?ronter des contraintes technologiques dans le cas des terminaux mobiles. La contrainte principale est la consommation de puissance du terminal. En e?et, la conversion analogique numérique qui est la clé de ce système en est aussi le principal verrou technique. Cette thèse présente une architecture de récepteur en rupture avec les architectures classiques a?n de surmonter le problème de la conversion analogique numérique. Il s’agit d’un processeur analogique de traitement du signal dédié à la Radio Logicielle intégrale dans la gamme de fréquence 0 à 5GHz. Sa conception et les mesures d’un prototype sont présentées. / Many technological bottlenecks prevent from realizing a Software Radio (SR) mobile terminal. The old way of building radio architectures is over due to the numerous communication standards a single handeld terminal have to address nowadays. This thesis exposes a disruptive SR receiver: a Sampled Analog Signal Processor (SASP) is designed and brought into play to perform downconversion and channel presort. It processes analog voltage samples in order to recover in baseband any RF signal emitted from 0 to 5GHz. An analog Fast Fourier Transform achieves both frequency shifting and ?ltering. A prototype using 65nm CMOS technology from STMicroelectronics is here presented and measured.

This work considers alternative strategies to mainstream digital approaches to signal processing - namely analog and neuromorphic solutions, for increased computing efficiency. In the context of a speech recognizer application, we use low-power analog approaches for the signal conditioning and basic auditory feature extraction, while using a neuromorphic IC for building a dendritic classifier that can be used as a low-power word spotter. In doing so, this work also aspires to posit the significance of dendrites in neural computation.

There is an ever increasing demand for higher spectral usage in wireless communication, radar and imaging systems. Higher spectral efficiency can be achieved using components that are aware of system environment and adapt suitably to the operating conditions. In this regard, radio frequency (RF) signal analysis is of paramount interest. Emergence of dispersive delay networks (DDN) has led to the significant development of microwave analogue-signal processing (ASP) and analysis. DDN causes displacement of spectral components in time domain, relative to the frequency dependant group delay response. The main challenge in the design of DDN in this context is in achieving broad bandwidth with high group delay dispersion (GDD). In this regard, all-pass networks (APN) have been explored as a potential wide-band DDN owing to the possibility of controlling the magnitude of loss characteristics without affecting the dispersion in group delay response. The synthesis procedure of lumped element APN using approximation methods is well known at audio frequencies. Most of these use operational amplifier and cannot be extended directly to RF. There is no generalised closed form analytical procedure at RF for the synthesis of APN with the required GDD. In this regard, this dissertation presents the design and implementation of all-pass networks as wide-band dispersive delay networks at radio frequencies. In this work, we begin by analysing the signal propagation through a DDN with a linear group delay response over a broad bandwidth. It is found that the signal experiences expansion of pulse width, reduction of its peak amplitude and a temporal displacement of the spectral components. Analytical expressions derived help initial synthesis of group delay response required for various ASP applications. As the first step towards implementation at RF, a single stage APN is designed using surface mount devices (SMD). This design approach takes into account practical issues such as parasitic due to mounting pads, available component values, physical dimensions, self-resonance frequency (SRF) and finite Q factor of the components used. Full wave simulation of the design with transmission line pads and components is carried out. This implementation is useful for frequencies up to the component SRF, generally about 5 GHz. This design approach makes the circuit footprint independent of frequency and the performance is limited only by the Q factor of the adopted technology. The Q factor affects the loss characteristics with a negligible effect on group delay response in the frequency band of interest. In order to extend the APN design for high group delay, a novel board level implementation is developed consisting of both lumped SMD components and distributed elements. The implementation results in a lower sensitivity of group delay performance to the commercially specified component value tolerances than the approach using all SMD components. It has been experimentally verified that the measured group delay is 2.4 ns at 1.85 GHz, which is thrice that reported in other approaches. The implementation has a reduced circuit footprint and is attractive in practical applications as it is a single layer micro strip realisation with less complex fabrication procedure and fewer components to assemble. As an extension of this towards wideband cascaded APN, an iterative design procedure is developed to achieve a monotonous group delay response over a broad bandwidth. The approach facilitates cascading of multiple stages of lumped APN with different resonance frequency and peak group delay to obtain linear and non-linear group delay responses with both positive and negative GDD. Circuits with both positive and negative GDD are required for various ASP applications such as compressive receivers and the present approach is unique in obtaining both the responses, not possible with many other RF dispersion techniques. Circuit models have been simulated by cascading transfer function responses of the individual APNs. The design is further extended for SMD implementation. To validate the above approach, a two stage APN is designed in the frequency range [0.5 - 1] GHz for a linear GDD of ±6 ns/GHz. Two negative GDD APNs are further cascaded to obtain a four stage implementation with an overall GDD of -12 ns/GHz. The experimental results are compared with full wave simulations for validation. The design using lumped SMD components has greatly improved the performance in terms of GDD with a reduced circuit footprint and lower insertion loss than previously reported approaches. As practical examples, the ASP modules are experimentally demonstrated using the fabricated APN. Frequency discrimination of two input frequencies with a frequency resolution of 500 MHz is demonstrated. Higher GDD results in higher separation of frequency components in time domain. Pulse compression and magnification is also demonstrated for different wideband LFM input signals. The dispersion effects of amplitude reduction, pulse width expansion and frequency chirping are thereby validated experimentally. In summary, the approaches presented in this dissertation enable the design of wideband all-pass networks to introduce dispersion delays over wide bandwidths, opening up the possibility for their use in analogue signal processing at radio frequencies. Some of these applications have been experimentally demonstrated and validated using time frequency analysis.

Le concept de Radio Logicielle propose d'intégrer en un seul circuit un émetteur / récepteur RF capable d'émettre et de recevoir n'importe quel signal RF. Cependant, ce concept doit affronter des contraintes technologiques dans le cas des terminaux mobiles. La contrainte principale est la consommation de puissance du terminal. En effet, la conversion analogique numérique qui est la clé de ce système en est aussi le principal verrou technique. Cette thèse présente une architecture de récepteur en rupture avec les architectures classiques afin de surmonter le problème de la conversion analogique numérique. Il s'agit d'un processeur analogique de traitement du signal dédié à la Radio Logicielle intégrale dans la gamme de fréquence 0 à 5GHz. Sa conception et les mesures d'un prototype sont présentées.

Demand for data communication capacity is rapidly increasing with more and more number of users and higher bandwidth services. As a result, a critical research issue is the implementation of wideband and flexible signal processing in communication and sensing applications. Although software defined radio (SDR) is a possible solution, it may not be practical due to the excessive requirements for analog-to-digital converter (ADCs) and digital filters for wideband signals. In this environment, discrete-time (DT) domain circuits are gaining attention in various architectures such as N-path filters, sampling mixers, and analog FIR/IIR/FFT filters. DT analog signal processing (DT-ASP) ahead of an ADC considerably relaxes the ADC requirements by flexible filtering, offers the potential for higher dynamic range performance, and provides robustness in the presence of digital CMOS scaling. The primary work presented in this dissertation is the design of wideband analog finite impulse response (AFIR) filters. Analog FIR filters have been used as low pass filters for out-of-band rejection in narrow-band applications. However, this work seeks to develop AFIR filters suitable for wideband applications, extending its possible applications. To achieve these performance goals, capacitive digital to analog converters (CDACs) have been introduced for the first time as wideband analog coefficient multipliers, which has led to high linearity analog multiplication with coefficient selection at the DAC resolution. A prototype 4th order DT FIR filter has been implemented in 32nm SOI CMOS technology and has achieved low-pass, band-pass, and high-pass filter (LPF, BPF and HPF) transfer functions corresponding to the programmed coefficient sets with IIP3>11dBm linearity and less than 2 mW/tap of power consumption. The AFIR filter is also utilized to demonstrate a proof-of-concept FIR-based beamforming. The beamforming network consisting of 4 antenna element inputs followed by AFIR filters was implemented with PCB modules with the previously fabricated AFIR filter chip. Behavioral simulations are used to verify the beamforming function with given coefficient sets. Based on the developed AFIR filter modules, FIR-based beamforming was demonstrated with measurement results matching well with the simulations. Further work presented is the design and optimization of multi-section CDAC (MS-CDAC) structures. The proposed MS-CDAC approach provides wide range of options to optimize the tradeoff between kT/C noise, linearity versus switching energy, speed and area. When the optimization approach is applied to a proof-of-concept 10-bit CDAC design, the selected MS-CDAC structure reduces total capacitance and switching energy by 97% and 98%, respectively for given linearity and noise limitations. The proposed MS-CDAC structures are applicable in both DT-ASP coefficient multiplier and SAR-ADC applications. / PHD / In communication systems, filter design is a fundamental task required to recover the signal of interest in the presence of interference. As upcoming communication systems, such as 5th generation (5G) mobile communications and future IEEE 802.11 standards (Wi-Fi), require higher speed and flexibility in signal processing due to the rapidly increasing number of users and data rates, it becomes more challenging to design such filters. In general, analog filters are useful for high-speed, digital filters features flexibility. To take advantage of both aspects, discrete-time (DT) domain filters have become a promising alternative, which can be used to implement digital signal processing functions in the analog domain. This dissertation presents the development of DT analog finite-impulse-response (AFIR) filter design for mixed-signal processing applications. The core idea in this work is to adopt the capacitive DAC (CDAC) as a coefficient multiplier, which enables digital code coefficient multiplication as well as high-speed and high-linearity performance while consuming low power. A prototype 4th order DT FIR filter implemented in 32nm SOI CMOS process is demonstrated with measurements. Based on the developed AFIR filters, proof-of-concept FIR-based beamforming is investigated as well. For this purpose, AFIR filter modules are built on printed-circuit-boards (PCBs) and coefficients are calculated by a simplified method. In addition, this dissertation also includes analysis and optimization of multi-section CDAC (MS-CDAC) structures. Traditional CDAC approaches have a fundamental trade-off between noise and linearity versus size, switching energy and speed. This work explores the characteristics of CDACs depending on the section segmentations and the optimal structure is selected based on the trade-off. Through comprehensive simulations and calculations, the selected structure for 10-bit MS-CDAC achieved 97% and 98% reduced total capacitance and switching energy, respectively.

This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation consists of two parts: Firstly, a fully-integrated arbitrary waveform generator for a multi-resolution spectrum sensing of a cognitive radio applications, and an analog matched-filter for a radar application and secondly, low-power techniques for an arbitrary waveform generator. The fully-integrated low-power AWG is implemented and measured in a 0.18-¥ìm CMOS technology. Theoretical analysis is performed, and the perspective implementation issues are mentioned comparing the measurement results. Moreover, the low-power techniques of SRAM are addressed for the analog signal processing: Self-deactivated data-transition bit scheme, diode-connected low-swing signaling scheme with a short-current reduction buffer, and charge-recycling with a push-pull level converter for power reduction of asynchronous design. Especially, the robust latch-type sense amplifier using an adaptive-latch resistance and fully-gated ground 10T-SRAM bitcell in a 45-nm SOI technology would be used as a technique to overcome the challenges in the upcoming deep-submicron technologies.

Αντικείμενο της παρούσας Ειδικής Επιστημονικής Εργασίας είναι η ανάπτυξη φίλτρων στο πεδίο της τετραγωνικής ρίζας με τη μέθοδο του γραμμικού μετασχηματισμού (Linear Transformation). Ως παράδειγμα, δίνεται η σχεδίαση, η εξομοίωση και τέλος η φυσική σχεδίαση ενός ελλειπτικού βαθυπερατού φίλτρου 3ης τάξης στο πεδίο της τετραγωνικής ρίζας (Square-Root Domain). Για λόγους σύγκρισης, η σχεδίαση του φίλτρου γίνεται με τέσσερις διαφορετικές μεθόδους εξομοίωσης παθητικών φίλτρων (Leapfrog, Topologic, Wave και Linear Trasformation method) και η ανάλυση κάθε μεθόδου παρουσιάζεται σε αντίστοιχο κεφάλαιο. / The subject of this master thesis is the design of analog filters in square root domain utilizing the method of Linear Transformation. As a design example a third order elliptic lowpass filter transfer function will be realized. For comparison results we are using four different design methods (Leapfrog, Topologic, Wave and Linear Trasformation)in order to realize such filter. Each synthesis method is demonstrated in different chapter.

Tato disertační práce pojednává o návrhu nových funkčních bloků použitelných v oblasti zpracování analogového signálu. Jde o obvody v proudové módu, které mohou ve vhodné konfiguraci pracovat v proudovém i v napěťovém módu. To umožnílo získat velmi nadějné výsledky v soustavách s nízkým napájecím napětím. Mnohostrannost těchto obvodů nalezne uplatnění v mnoha aplikacích. Zesilovač s proudovou zpětnou vazbou byl zavolen jako hlavní stavební blok pro detailní zkoumání funkce obvodů s RC operační sítí. Tato disertační práce pojednává o studiu, syntéze a návrhových aspektech realizace nových imitančních funkcí, jmenovitě induktivních a superkapacitních, proudových a napěťových konvejorech, kmitočtových filtrech s velkou jakostí, integrátorech a diferenciátorech, fázovacích členech s neminimální fází a napětím řízených oscilátorech. Disertační práce se detailně zabývá těmito novými bloky, které jsou popsány teoreticky a vyhodnoceny na základě simulací vlastností.