In this work, a programmable frequency divider suitable for millimeter wave
phase-lock loops is presented. The frequency divider has been implemented in a
90 nm standard CMOS technology. To the extent of maximizing the operative input
frequency, the higher frequency digital blocks of the frequency divider have been
realized using dynamic precharge-evaluation logic. Moreover, a non-conventional
method to implement non-power-of-2 division ratios has been used for the higher
frequency divider stages (input stages).
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/24610 |
| Date | 16 June 2008 |
| Creators | Barale, Francesco |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Detected Language | English |
| Type | Thesis |
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