MEMS Sensors are widely used for sensing inertial displacements. The displacements arising out of acceleration /Coriolis effect are typically in the range of 1 nm-1 m. This work investigates the realization of high resolution MEMS inertial sensors using novel displacement sensing mechanisms.
Capacitance sensing ASIC is developed as part of conventional electronics interface with MEMS sensor under the conventional CMOS-MEMS integration strategy. The capacitance sense ASIC based on Continuous Time Voltage scheme with coherent and non-coherent demodulation is prototyped on AMS 0.35 m technology. The ASIC was tested to sense C = 3.125 fF over a base of 2 pF using on-chip built-in test capacitors. Dynamic performance of this ASIC was validated by interfacing with a DaCM MEMS accelerometer. 200milli-g of acceleration (equivalent to a C = 2.8 fF) over an input frequency of 20Hz is measurable using the developed ASIC. The observed sensitivity is 90mV/g. The ASIC has several programmable features such as variation in trim capacitance (3.125 fF-12.5 pF), bandwidth selection (500 Hz-20 kHz) and variable gain options (2-100).
Capacitance detection, a dominant sensing principle in MEMs sensors, experiences inherent limitation due to the role of parasitics when the displacements of interest are below 5 nm range. The capacitive equivalence ( C) for the range of displacements of the order of 5 nm and below would vary in the range atto-to-zepto farad. Hence there is a need to explore alternative sensing schemes which preferably yield higher sensitivity (than those offered by the conventional integration schemes) and are based on the principle of built-in transduction to help overcome the influence of parasitics on sensitivity.
In this regard, 3 non-conventional architectures are explored which fall under the direct integration classification namely:
(a) Sub-threshold based sensing
(b) Fringe field based sensing and
(c) Tunneling current based sensing.
a) In Sub-threshold based sensing, FET with a suspended gate is used for displacement sensing. The FET is biased in the sub-threshold region of operation. The exponential modulation of drain current for a change in displacement of 1 nm is evaluated using TCAD, and the in uence of initial air-gap variation on the sensitivity factor ( ID=ID) is brought out.
For 1% change in air gap displacement (i.e., TGap/TGap, the gap variation resulting due to the inertial force / mass loading) nearly 1050% change in drain current( ID=ID) is observed (considering initial air gaps of the order 100 nm). This validates the high sensitivity offered by the device in this regime of operation. A comparison of sensitivity estimate using the capacitive equivalence model and TCAD simulated model for different initial air-gaps in a FD-SOI FET is brought out. The influence of FDSOI FET device parameters on sensitivity, namely the variation of TSi, TBox, NA and TGap are explored.
CMOS compatibility and fabrication feasibility of this architecture was looked into by resorting to the post processing approach used for validating the sub-threshold bias concept. The IMD layers of the Bulk FETs fabricated through AMS 0.35 technology were etched using BHF and IPA mixture to result in a free standing metal (Al) layers acting as the suspended gate. The performance estimate is carried out considering specific Equivalent Gap Thickness (EGT) of 573 nm and 235 nm, to help overcome the role of coupled electrostatics in influencing the sensitivity metric. The sensitivity observed by biasing this post processed bulk FET in sub-threshold is 114% ( ID=ID change) for a 59% ( d/d change). The equivalent C in this case is 370 aF.
b) In Fringe eld based sensing approach, a JunctionLess FET (JLFET) is used as a depletion mode device and an out-of-plane gate displacement would help modulate the device pinch-o voltage due to fringe field coupling. The resulting change in the gate fringe field due to this displacement modulates the drain current of the JunctionLess FET. The displacement induced fringe field change (relative to the FET channel) brings about a distinct shift in the ID-VG characteristics of the JLFET. For displacement
d = 2 nm, the JLFET with a channel doping of ND = 8X1018cm 3 and a bias point of VG = -47.7 V, 98% enhancement in sensitivity is observed in 3D TCAD simulations. The equivalent C in this case is 29 zF. The role of ground-planes in the device operation is explored.
c) In the tunneling current based sensing approach, the beams fabricated using the SOI-MUMPS process are FIB milled so as to create very ne air gaps of the order of nearly 85 nm. Under high electric fields of the order > 8 MV/cm, the lateral displacement based tunneling sensor offers enhanced change in sensitivity for an induced external force at a fixed DC bias. When integrated as an array with varying electrode overlap, this technique can track displacements over a wide range. With the initial beam overlap as 1.2 m, for a lateral displacement of 1.2 m, a 100% change in sensitivity ( ID=ID) is observed. The effect of fringe field can be completely neglected here unlike its capacitive beam equivalent.
| Identifer | oai:union.ndltd.org:IISc/oai:etd.ncsi.iisc.ernet.in:2005/2760 |
| Date | January 2015 |
| Creators | Thejas, * |
| Contributors | Bhat, Navakanta |
| Source Sets | India Institute of Science |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
| Relation | G26884 |
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