Integrated circuit development is an industry-driven high-risk high-stakes environment. The time from the concept of a new transistor technology to the market-ready product is measured in decades rather than months or years. This increases the risk for any company endeavouring on the journey of driving a new concept. Additionally to the return on investment being in the far future, it is only to be expected at all in high volume production, increasing the upfront investment. What makes the undertaking worthwhile are the exceptional gains that are to be expected, when the production reaches the market and enables better products. For these reasons, the adoption of new transistor technologies is usually based on small increments with foreseeable impact on the production process. Emerging semiconductor device development must be able to prove its value to its customers, the chip-producing industry, the earlier the better. With this thesis, I provide a new approach for early evaluation of emerging reconfigurable transistors in reconfigurable digital circuits. Reconfigurable transistors are a type of MOSFET that features a controllable conduction polarity, i.e., they can be configured by other input signals to work as PMOS or NMOS devices.
Early device and circuit characterisation poses some challenges that are currently largely neglected by the development community. Firstly, to drive transistor development into the right direction, early feedback is necessary, which requires a method that can provide quantitative and qualitative results over a variety of circuit designs and must run mostly automatic. It should also require as little expert knowledge as possible to enable early experimentation on the device and new circuit designs together. Secondly, to actually run early, its device model should need as little data as possible to provide meaningful results. The proposed approach of this thesis tackles both challenges and employs model checking, a formal method, to provide a framework for the automated quantitative and qualitative analysis. It pairs a simple transistor device model with a charge transport model of the electrical network.
In this thesis, I establish the notion of transistor-level reconfiguration and show the kinds of reconfigurable standard cell designs the device facilitates. Early investigation resulted in the discovery of certain modes of reconfiguration that the transistor features and their application to design reconfigurable standard cells. Experiments with device parameters and the design of improved combinational circuits that integrate new reconfigurable standard cells further highlight the need for a thorough investigation and quantification of the new devices and newly available standard cells. As their performance improvements are inconclusive when compared to established CMOS technology, a design space exploration of the possible reconfigurable standard cell variants and a context-aware quantitative analysis turns out to be required.
I show that a charge transport model of the analogue transistor circuit provides the necessary abstraction, precision and compatibility with an automated analysis. Formalised in a DSL, it enables designers to freely characterise and combine parametrised transistor models, circuit descriptions that are device independent, and re-usable experiment setups that enable the analysis of large families of circuit variants. The language is paired with a design space exploration algorithm that explores all implementation variants of a Boolean function that employs various degrees and modes of reconfiguration. The precision of the device models and circuit performance calculations is validated against state-of-the-art FEM and SPICE simulations of production transistors.
Lastly, I show that the exploration and analysis can be done efficiently using two important Boolean functions. The analysis ranges from worst-case measures, like delay, power dissipation and energy consumption to the detection and quantification of output hazards and the verification of the functionality of a circuit implementation. It ends in presenting average performance results that depend on the statistical characterisation of application scenarios. This makes the approach particularly interesting for measures like energy consumption, where average results are more interesting, and for asynchronous circuit designs which highly depend on average delay performance. I perform the quantitative analysis under various input and output load conditions in over 900 fully automated experiments. It shows that the complexity of the results warrants an extension to electronic design automation flows to fully exploit the capabilities of reconfigurable standard cells. The high degree of automation enables a researcher to use as little as a Boolean function of interest, a transistor model and a set of experiment conditions and queries to perform a wide range quantitative analyses and acquire early results.:1 Introduction
1.1 Emerging Reconfigurable Transistor Technology
1.2 Testing and Standard Cell Characterisation
1.3 Research Questions
1.4 Design Space Exploration and Quantitative Analysis
1.5 Contribution
2 Fundamental Reconfigurable Circuits
2.1 Reconfiguration Redefined
2.1.1 Common Understanding of Reconfiguration
2.1.2 Reconfiguration is Computation
2.2 Reconfigurable Transistor
2.2.1 Device geometry
2.2.2 Electrical properties
2.3 Fundamental Circuits
3 Combinational Circuits and Higher-Order Functions
3.1 Programmable Logic Cells
3.1.1 Critical Path Delay Estimation using Logical Effort Method
3.1.2 Multi-Functional Circuits
3.2 Improved Conditional Carry Adder
4 Constructive DSE for Standard Cells Using MC
4.1 Principle Operation of Model Checking
4.1.1 Model Types
4.1.2 Query Types
4.2 Overview and Workflow
4.2.1 Experiment setup
4.2.2 Quantitative Analysis and Results
4.3 Transistor Circuit Model
4.3.1 Direct Logic Network Model
4.3.2 Charge Transport Network Model
4.3.3 Transistor Model
4.3.4 Queries for Quantitative Analysis
4.4 Circuit Variant Generation
4.4.1 Function Expansion
5 Quantitative Analysis of Standard Cells
5.1 Analysis of 3-Input Minority Logic Gate
5.1.1 Circuit Variants
5.1.2 Worst-Case Analysis
5.2 Analysis of 3-Input Exclusive OR Gate
5.2.1 Worst-Case Analysis
5.2.2 Functional Verification
5.2.3 Probabilistic Analysis
6 Conclusion and Future Work
6.1 Future Work
A Notational conventions
B prism-gen Programming Interfaces
Bibliography
Terms & Abbreviations
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:82769 |
| Date | 22 December 2022 |
| Creators | Raitza, Michael |
| Contributors | Kumar, Akash, Mikolajick, Thomas, Amrouch, Hussam, Technische Universität Dresden |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | info:eu-repo/semantics/publishedVersion, doc-type:doctoralThesis, info:eu-repo/semantics/doctoralThesis, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | 10.5555/2971808.2971846, 10.23919/DATE.2017.7927013, 10.1109/TVLSI.2018.2884646, 10.1109/ACCESS.2020.3001352, 10.23919/DATE54114.2022.9774620 |
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