The carbon nanotube-based field effect transistor (CNTFET) possesses the potential to overcome limitations of state-of-the-art technologies such as silicon-based complementary metal-oxide-semiconductors. However, the carbon nanotube (CNT) technology is still at its infancy and technology development is still necessary to exploit the CNT properties such as high charge carrier mobility, high current carrying capability, one-dimensional charge transport and their versatile integrability.
Within this work significant progress has been achieved scientifically and technologically in the advance of high frequency (HF) CNTFETs for analog applications. According to simulations by others, a technology flow has been developed based on electron beam lithography for bottom gated HF CNTFETs which outperform state-of the art top gate architectures with respect to their parasitic capacitances.
Moreover, the impact of electrostatic doping on the CNTFETs has been investigated. In particular, the dynamics of water desorption from the CNTFETs and the related reduction of p-type doping was investigated and the different impact of the n-type dopant polyethylenimine onto the channel region and contact region could be separated for the first time. Furthermore, the impact of doped CNT bundles on the device performance has been studied. It could be shown in detail for the first time, that high off-state source-drain leakage currents can be due to bundled semiconducting CNTs and does not necessarily imply the presence of metallic CNTs. The within the framework of this thesis designed and realized HF CNTFETs are operating in the GHz range with cut-off frequencies up to 14 GHz and maximum frequencies of oscillation up to 6 GHz at a channel length of 280 nm. Moreover, the impact of the spacer between the source-/ drain- to the gate electrode on the HF properties of the CNTFETs has been investigated experimentally for the first time. Simulations by others have successfully confirmed that a symmetrical reduction of the source to gate electrode spacer results in an increased device speed. By asymmetrically reducing the source to gate electrode spacer and in parallel increasing the drain-to-gate electrode spacer the device speed can be further enhanced. Moreover, within this work it has been experimentally indicated for the first time that the device properties of HF CNTFETs can be tuned by different device geometries towards either highest linearity or speed.
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:82657 |
| Date | 04 January 2023 |
| Creators | Hartmann, Martin |
| Contributors | Kuhn, Harald, Schröter, Michael, Technische Universität Chemnitz |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | info:eu-repo/semantics/publishedVersion, doc-type:doctoralThesis, info:eu-repo/semantics/doctoralThesis, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
Page generated in 0.0025 seconds