Kwok Yan-lun Andy. / Thesis submitted in: November 2004. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 133-137). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.ii / Acknowledgements --- p.iii / List of Figures --- p.vii / List of Tables and Examples --- p.x / Chapter 1. --- Introduction --- p.1 / Chapter 1.1. --- Motivation --- p.1 / Chapter 1.2. --- Objective and Approach --- p.4 / Chapter 1.3. --- Thesis Organization --- p.5 / Chapter 2. --- Related Work --- p.7 / Chapter 2.1. --- Coverage --- p.7 / Chapter 2.2. --- ASIP Design Methodologies --- p.8 / Chapter 2.3. --- Asynchronous Technology on Processors --- p.12 / Chapter 2.4. --- Summary --- p.14 / Chapter 3. --- Asynchronous Design Methodology --- p.15 / Chapter 3.1. --- Overview --- p.15 / Chapter 3.2. --- Asynchronous Design Style --- p.17 / Chapter 3.2.1. --- Micropipelines --- p.17 / Chapter 3.2.2. --- Fine-grain Pipelining --- p.20 / Chapter 3.2.3. --- Globally-Asynchronous Locally-Synchronous (GALS) Design --- p.22 / Chapter 3.3. --- Advantages of GALS in ASIP Design --- p.27 / Chapter 3.3.1. --- Reuse of Synchronous and Asynchronous IP --- p.27 / Chapter 3.3.2. --- Fine Tuning of Performance and Power Consumption --- p.27 / Chapter 3.3.3. --- Synthesis-based Design Flow --- p.28 / Chapter 3.4. --- Design of GALS Asynchronous Wrapper --- p.28 / Chapter 3.4.1. --- Handshake Protocol --- p.28 / Chapter 3.4.2. --- Pausible Clock Generator --- p.29 / Chapter 3.4.3. --- Port Controllers --- p.30 / Chapter 3.4.4. --- Performance of the Asynchronous Wrapper --- p.33 / Chapter 3.5. --- Summary --- p.35 / Chapter 4. --- Platform Based ASIP Design Methodology --- p.36 / Chapter 4.1. --- Platform Based Approach --- p.36 / Chapter 4.1.1. --- The Definition of Our Platform --- p.37 / Chapter 4.1.2. --- The Definition of the Platform Based Design --- p.37 / Chapter 4.2. --- Platform Architecture --- p.38 / Chapter 4.2.1. --- The Nature of DSP Algorithms --- p.38 / Chapter 4.2.2. --- Design Space of Datapath Optimization --- p.46 / Chapter 4.2.3. --- Proposed Architecture --- p.49 / Chapter 4.2.4. --- The Strategy of Realizing an Optimized Datapath --- p.51 / Chapter 4.2.5. --- Pipeline Organization --- p.59 / Chapter 4.2.6. --- GALS Partitioning --- p.61 / Chapter 4.2.7. --- Operation Mechanism --- p.63 / Chapter 4.3. --- Overall Design Flow --- p.67 / Chapter 4.4. --- Summary --- p.70 / Chapter 5. --- Design of the ASIP Platform --- p.72 / Chapter 5.1. --- Design Goal --- p.72 / Chapter 5.2. --- Instruction Fetch --- p.74 / Chapter 5.2.1. --- Instruction fetch unit --- p.74 / Chapter 5.2.2. --- Zero-overhead loops and Subroutines --- p.75 / Chapter 5.3. --- Instruction Decode --- p.77 / Chapter 5.3.1. --- Instruction decoder --- p.77 / Chapter 5.3.2. --- The Encoding of Parallel and Complex Instructions --- p.80 / Chapter 5.4. --- Datapath --- p.81 / Chapter 5.4.1. --- Base Functional Units --- p.81 / Chapter 5.4.2. --- Functional Unit Wrapper Interface --- p.83 / Chapter 5.5. --- Register File Systems --- p.84 / Chapter 5.5.1. --- Memory Hierarchy --- p.84 / Chapter 5.5.2. --- Register File Organization --- p.85 / Chapter 5.5.3. --- Address Generation --- p.93 / Chapter 5.5.4. --- Load and Store --- p.98 / Chapter 5.6. --- Design Verification --- p.100 / Chapter 5.7. --- Summary --- p.104 / Chapter 6. --- Case Studies --- p.105 / Chapter 6.1. --- Objective --- p.105 / Chapter 6.2. --- Approach --- p.105 / Chapter 6.3. --- Based versus Optimized --- p.106 / Chapter 6.3.1. --- Matrix Manipulation --- p.106 / Chapter 6.3.2. --- Autocorrelation --- p.109 / Chapter 6.3.3. --- CORDIC --- p.110 / Chapter 6.4. --- Optimized versus Advanced Commercial DSPs --- p.113 / Chapter 6.4.1. --- Introduction to TMS320C62x and SC140 --- p.113 / Chapter 6.4.2. --- Results --- p.115 / Chapter 6.5. --- Summary --- p.116 / Chapter 7. --- Conclusion --- p.118 / Chapter 7.1. --- When ASIPs encounter asynchronous --- p.118 / Chapter 7.2. --- Contributions --- p.120 / Chapter 7.3. --- Future Directions --- p.121 / Chapter A --- Synthesis of Extended Burst-Mode Asynchronous Finite State Machine --- p.122 / Chapter B --- Base Instruction Set --- p.124 / Chapter C --- Special Registers --- p.127 / Chapter D --- Synthesizable Model of GALS Wrapper --- p.130 / Reference --- p.133
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_325192 |
| Date | January 2005 |
| Contributors | Kwok, Yan-lun Andy., Chinese University of Hong Kong Graduate School. Division of Electronic Engineering. |
| Source Sets | The Chinese University of Hong Kong |
| Language | English, Chinese |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, x, 137 leaves : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
Page generated in 0.0021 seconds