Energy harvesting technologies are crucial for the future green transition. Research shows the versatility and efficiency of integrated energy harvesting solutions. Economic advantages, enhanced energy efficiency, and reduced reliance on conventional power sources can be achieved with well implemented systems. Furthermore, there are environmental benefits from using more renewable energy sources due to fewer emissions from battery production and replacement. One of the challenges with system implementation is achieving high efficiency for various energy sources and system loads. This study aimed to showcase the design steps for crucial system blocks to aid in designing complete energy harvesting systems. The designs are done in a 180 nm CMOS process. A literature study, including recent research on capacitive and inductive converters, gave insight into the limitations of the different topologies. The study also included other crucial blocks for efficient energy harvesting systems, such as Maximum power point tracking and cold-start. In the study, commercially available energy harvesting chips are discussed, and it is concluded that the market is limited regarding alternatives for a wide range of systems. A microcontroller is needed for an adaptable system. For the study, an additional aim was to provide support for an MSP430L092, a low-power microcontroller from Texas Instruments. The support included level shifters and supply voltage generation. Due to time constraints, not all blocks were designed. The designed blocks are a boost converter, level shifters and a Pulse-width modulation generation network composed of a comparator and oscillator. Other blocks needed in efficient energy harvesting systems are included as short discussions of possible implementations from other research and commercially available components. Simulation of the boost converter showed that the main losses are from the non ideal inductor. These were minimised by using a higher switching frequency of 1 MHz and allowing a larger inductor ripple current, which allowed for a smaller inductor. From a 500 mV input voltage boosting to a 2 V output voltage with a constant output power of 120 μW an efficiencyof 88.36% was achieved. A high efficiency was achieved down to 300 mV of input voltage. In the pulse-width modulation network simulation, the main losses were found to be from the current spikes in the buffering stages. Higher voltage threshold transistors and smaller widths minimised these issues. Simulation at 1 MHz showed a power consumption of 5 μW for the complete network and a duty cycle range of 28% to 91%. The comparators standalone power consumption was simulated to 2.3 μW. Some deviations from calculations were noted in the oscillator circuit, which was concluded to be an issue due to the heavy power optimisation. It was not investigated any further in this work but left as future work to investigate the comparator further. From simulated data and datasheets, an estimation for the total combined system efficiency is calculated to be 71.3%. Future work includes the layout of the designed blocks to evaluate the impact of the parasitic extraction.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:ltu-108204 |
| Date | January 2024 |
| Creators | Axenhag, Johan |
| Publisher | Luleå tekniska universitet, Institutionen för system- och rymdteknik |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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