The realisation of signal processing algorithms in fixed-point offers substantial performance advantages over floating-point realisations. However, it is widely acknowledged that the task of realising algorithms in fixed-point is a challenging one with limited tool support. This thesis examines various aspects related to the translation of algorithms, given in infinite precision or floating-point, into fixed-point. In particular, this thesis reports on the implementation of a given algorithm, an EDFA (Erbium-Doped Fibre Amplifier) control algorithm, on a FPGA (Field Programmable Gate Array) using fixed-point arithmetic. An analytical approach is proposed that allows the automated realisation of algorithms in fixedpoint. The technique provides fixed-point parameters for a given floating-point model that satisfies a precision constraint imposed on the primary output of the algorithm to be realised. The development of a simulation framework based on this analysis allows fixed-point designs to be generated in a shorter time frame. Albeit being limited to digital algorithms that can be represented as a data flow graph (DFG), the approach developed in the thesis allows for a speed up in the design and development cycle, reduces the possibility of error and eases the overall effort involved in the process. It is shown in this thesis that a fixed-point realisation of an EDFA control algorithm using this technique produces results that satisfy the given constraints.
| Identifer | oai:union.ndltd.org:ADTP/246431 |
| Date | January 2009 |
| Creators | Wijaya, Shierly |
| Publisher | University of Western Australia. School of Electrical, Electronic and Computer Engineering |
| Source Sets | Australiasian Digital Theses Program |
| Language | English |
| Detected Language | English |
| Rights | Copyright Shierly Wijaya, http://www.itpo.uwa.edu.au/UWA-Computer-And-Software-Use-Regulations.html |
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