Since its introduction in the 1980s, field-programmable gate arrays have seen a growing use over the years. Nowadays FPGAs are found in everything from planetary rovers and base transceiver stations to bitcoin miners. With the technological advancements and the growth of the market, there has been a steady flow of new models with increasing capacity. To make it possible to use this capacity in an efficient way, also the software tools have been improved. The applications in research have grown and so has the will to compare both the speed and size between different implementations that try to solve the same or similar problem. However, how to make a good comparison is not well defined. Since few research papers have source code available, such comparisons are hard to make and there is a high risk of comparing apples to pears. In this thesis, we will study the impact of different software settings and design constraints on the FPGA design flows to better understand how to report research results. This will be done by running selected designs through different EDA tools, using various settings and finally analyse the data the tools provide. At the end we will begin to define guidelines for how to report and compare implementation data, to give a good account of their performance compared to other designs.

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The Lower Atmosphere/Ionosphere Coupling Experiment (LAICE) CubeSat mission includes the payload instruments that generate scientific data by interacting with the flight computer. The LAICE Instrument Interface Board (LIIB) is designed to interface with the payload instruments and the flight computer for efficient operation of the LAICE. The uplink command packet contains commands for regulating power supply to the payload instruments and for interfacing the peripheral, called the thermal knife, with the science instruments. The LIIB is responsible for interpreting these commands in order to execute the associated functions. The architecture of the LIIB is designed such that it not only takes into account all the requirements of the systems and instruments on the LAICE, but also ensures smooth flight data analysis at the ground station end. The approach taken to build the design makes the entire process intuitive and easier to debug. This thesis describes the design and development of the LIIB firmware, to ensure proper functioning of the LAICE. The firmware design is presented first, by initially defining the architecture based on the system requirements and progressing eventually to its development at the system level. End-to-end testing with the payload instruments and thermal knife setup verifies the operation of the LAICE LIIB firmware and electronics, thus qualifying the instrument for deployment within the LAICE. / Master of Science

Free Space Optical (FSO) satellite communications is proving to be a key enabling technology for global connectivity with the ability to provide connection across Europe with only 12 ground stations. For this, Deutsches Zentrum für Luft- und Raumfahrt (DLR) is working on implementing a robust communication system for FSO on a Xilinx RFSoC Field Programmable Gate Array (FPGA)( ZU28DR). However, FSO is susceptible to deep fades and atmospheric turbulence affecting the quality of the communication system. Thus, measuring the performance of the communication system is crucial for choosing system parameters and designing new blocks to enhance the performance. In this thesis, a high speed test-bed implementation exploiting Parallel Pseudo Random Binary Sequence (PRBS) to measure the performance of the system is implemented. The test-bed is designed to mitigate channel fading problems to correctly calculate the Bit Error Rate (BER). The test-bed is designed to allow for online adjustment of the communication system to facilitate parameter optimizations. / FSO-satellitkommunikation visar sig vara en viktig teknologi för global anslutning med förmågan att tillhandahålla anslutning över Europa med endast 12 markstationer. För detta arbetar DLR med att implementera ett robust kommunikationssystem för FSO på en Xilinx RFSoC FPGA (ZU28DR). Men FSO är känsligt för djupa fades och atmosfärisk turbulens som påverkar kvaliteten på kommunikationssystemet. Därför är mätningen av systemets prestanda avgörande för att välja systemparametrar och designa nya block för att förbättra prestanda. I denna avhandling implementeras en höghastighets testbädd som utnyttjar parallel PRBS för att mäta systemets prestanda. Testbädden är designad för att motverka kanalförlustproblem för att korrekt beräkna BER. Testbädden är designad för att tillåta justering av kommunikationssystemet online för att underlätta optimering av parametrar

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Throughout the history of software development, advances have been made that improve the ability of developers to create systems by enabling them to work closer to their application domain. These advances have given programmers higher level abstractions with which to reason about problems. A separation of concerns between logic and implementation allows for reuse of components, portability between implementation platforms, and higher productivity. Parallels can be drawn between the challenges that the field of reconfigurable computing (RC) is facing today and what the field of software engineering has gone through in the past. Most RC work is done in low level hardware description languages (HDLs) at the circuit level. A large productivity gap exists between the ability of RC developers and the potential of the technology. The small number of RC experts is not enough to meet the demands for RC applications. Model-based engineering principles provide a way to reason about RC devices at a higher level, allowing for greater productivity, reuse, and portability. Higher level abstractions allow developers to deal with larger and more complex systems. A modeling environment has been developed to aid users in creating models, storing, reusing and generating hardware implementation code for their system. This environment serves as a starting point to apply model-based techniques to the field of RC to tighten the productivity gap. Future work can build on this model-based framework to take advantage of the unique features of reconfigurable devices, optimize their performance, and further open the field to a wider audience. / Master of Science

Engineers often view variability as undesirable and seek to minimize it, such as when they employ transistor-matching techniques to improve circuit and system performance. Biology, however, makes no discernible attempt to avoid this variability, which is particularly evident in biological nervous systems whose neurons exhibit marked variability in their cellular properties. In previous studies, this heterogeneity has been shown to have mixed consequences on network rhythmicity, which is essential to locomotion and other oscillatory neural behaviors. The systems that produce and control these stereotyped movements have been optimized to be energy efficient and dependable, and one particularly well-studied rhythmic network is the central pattern generator (CPG), which is capable of generating a coordinated, rhythmic pattern of motor activity in the absence of phasic sensory input. Because they are ubiquitous in biological preparations and reveal a variety of physiological behaviors, these networks provide a platform for studying a critical set of biological control paradigms and inspire research into engineered systems that exploit these underlying principles. We are directing our efforts toward the implementation of applicable technologies and modeling to better understand the combination of these two concepts---the role of heterogeneity in rhythmic networks of neurons. The central engineering theme of our work is to use digital and analog platforms to design and build Hodgkin--Huxley conductance-based neuron models that will be used to implement a half-center oscillator (HCO) model of a CPG. The primary scientific question that we will address is to what extent this heterogeneity affects the rhythmicity of a network of neurons. To do so, we will first analyze the locations, continuities, and sizes of bursting regions using single-neuron models and will then use an FPGA model neuron to study parametric and topological heterogeneity in a fully-connected 36-neuron HCO. We found that heterogeneity can lead to more robust rhythmic networks of neurons, but the type and quantity of heterogeneity and the population-level metric that is used to analyze bursting are critical in determining when this occurs.

Echo State Network (ESN) is a recently developed machine-learning paradigm whose processing capabilities rely on the dynamical behavior of recurrent neural networks (RNNs). Its performance metrics outperform traditional RNNs in nonlinear system identification and temporal information processing. In this thesis, we design and implement ESNs through Field-programmable gate array (FPGA) and explore their full capacity of digital signal processors (DSPs) to target low-cost and low-power applications. We propose a cost-optimized and scalable ESN architecture on FPGA, which exploits Xilinx DSP48E1 units to cut down the need of configurable logic blocks (CLBs). The proposed work includes a linear combination processor with negligible deployment of CLBs, as well as a high-accuracy non-linear function approximator, both with the help of only 9 DSP units in each neuron. The architecture is verified with the classical NARMA dataset, and a symbol detection task for an orthogonal frequency division multiplexing (OFDM) system on a wireless communication testbed. In the worst-case scenario, our proposed architecture delivers a matching bit error rate (BER) compares to its corresponding software ESN implementation. The performance difference between the hardware and software approach is less than 6.5%. The testbed system is built on a software-defined radio (SDR) platform, showing that our work is capable of processing the real-world data. / Master of Science / Machine learning is a study of computer algorithms that evolves itself by learning through experiences. Currently, machine learning thrives as it opens up promising opportunities of solving the problems that is difficult to deal with conventional methods. Echo state network (ESN), a recently developed machine-learning paradigm, has shown extraordinary effectiveness on a wide variety of applications, especially in nonlinear system identification and temporal information processing. Despite the fact, ESN is still computationally expensive on battery-driven and cost-sensitive devices. A fast and power-saving computer for ESN is desperately needed. In this thesis, we design and implement an ESN computational architecture through the field-programmablegate array (FPGA). FPGA allows designers to build highly flexible customized hardware with rapid development time. Our design further explores the full capacity of digital signal processors (DSP) on Xilinx FPGA to target low-cost and low-power applications. The proposed cost-optimized and scalable ESN architecture exploits Xilinx DSP48E1 units to cut down the need of configurable logic blocks (CLBs). The work includes a linear combination processor with negligible deployment of CLBs, and a high-accuracy non-linear function approximator, both with the help of only 9 DSP units in each neuron. The architecture is verified with the classical NARMA dataset, and a symbol detection task for an orthogonal frequency division multiplexing (OFDM) system in a wireless communication testbed. In the worst-case scenario, our proposed architecture delivers a matching bit error rate (BER) compares to its corresponding software ESN implementation. The performance difference between the hardware and software approach is less than 6.5%. The testbed system is built on a software-defined radio (SDR) platform, showing that our work is capable of processing the real-world data.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2011. / ENGLISH ABSTRACT: The development of an integrated avionics system containing all the required sensors and actuators for autopilot control is presented. The thesis analyzes the requirements for the system and presents detailed hardware design. The architecture of the system is based on an FPGA which is tasked with interfacing with the sensors and actuators. The FPGA abstracts a microprocessor from these interface modules, allowing it to focus only on the control and user interface algorithms. Firmware design for the FPGA, as well as a conceptualization of the microprocessor software design is presented. Simulation results showing the functionality of firmware modules are presented. / AFRIKAANSE OPSOMMING: Die ontwikkeling van ‘n geïntegreede avionika‐stelsel wat al die vereiste sensors en aktueerders vir outoloods‐beheer bevat, word voorgestel. Die tesis analiseer die vereistes van die stelsel en stel ‘n hardeware‐ontwerp voor. Die argitektuur van die stelsel bevat ‘n FPGA wat ‘n koppelvlak met sensors en aktueerders skep. Die FPGA verwyder die mikroverwerker weg van hierdie koppelvlak modules en stel dit sodoende in staat om slegs op die beheer en gebruikerskoppelvlak‐algoritmes te fokus. Sagteware‐ontwerp vir die FPGA, asook die konseptualisering van die sagtewareontwerp vir die mikroverwerker, word aangebied. Simulasie resultate wat die funksionaliteit van die FPGA‐sagteware modules aandui, word ook voorgestel.

Goal of the diploma thesis is a design of fast memory module and to introduce myself with issues involved in data storage in memory of high speed camera. The work is concerned about two designs adding memory capacity of high speed camera with DDR3 memory modules. For production is selected the more suitable design that is better for commercial purposes. The main objective is to design a schematic with FPGA as a main controller, that will operate data flow from CMOS sensor to superior development board MicroZed. Final design should allow us to sell the high speed camera as a separate unit.