FPGAs provide parallel computing that is fit for speeding up the computation of a large range of problems. Programming an FPGA involves a complex tool flow for which several CAD tools have been developed. These tools compute solutions to many problems such as packing, placement, and routing, which map a circuit design onto an FPGA. These computations require a great deal of memory, of which the Routing Resource Graph contributes the most of any individual data structure. If the RRGraph could be represented in a more compact manner, performance of the tool flow algorithms may be improved due to an increase in memory caching benefits. This work presents four variations on RRGraph folding which vary in memory usage reduction and runtime, with the most aggressive method reducing the RRGraph size by up to 4x while maintaining similar performance to the original representation.
| Identifer | oai:union.ndltd.org:BGMYU2/oai:scholarsarchive.byu.edu:etd-10423 |
| Date | 07 April 2022 |
| Creators | Rogers, Ethan Steiner |
| Publisher | BYU ScholarsArchive |
| Source Sets | Brigham Young University |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Theses and Dissertations |
| Rights | https://lib.byu.edu/about/copyright/ |
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