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Academic Clustering and Placement Tools for Modern Field-programmable Gate Array Architectures

Academic Clustering and Placement Tools
for Modern Field-Programmable Gate Array Architectures
Daniele Giuseppe Paladino
Masters of Applied Science
Graduate Department of Electrical and Computer Engineering
University of Toronto
2008


Abstract

Academic tools have been used in many research studies to investigate Field-Programmable Gate Array (FPGA) architecture, but these tools are not sufficiently flexible to represent modern commercial devices. This thesis describes two new tools, the Dynamic Clusterer (DC) and the Dynamic Placer (DP) that perform the clustering and placement steps in the FPGA CAD flow. These tools are developed in direct extension of the popular Versatile Place and Route (VPR) academic tools. We describe the changes that are necessary to the traditional tools in order to model modern devices, and provide experimental results that show the quality of the algorithms achieved is similar to a commercial CAD tool, Quartus II. Finally, a small number of research experiments were investigated using the clustering and placement tools created to demonstrate the practical use of these tools for academic research studies of FPGA CAD tools.

Identiferoai:union.ndltd.org:TORONTO/oai:tspace.library.utoronto.ca:1807/11159
Date30 July 2008
CreatorsPaladino, Daniele Giuseppe
ContributorsBrown, Stephen
Source SetsUniversity of Toronto
Languageen_ca
Detected LanguageEnglish
TypeThesis
Format878889 bytes, application/pdf

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