Return to search

A Verilog 8051 Soft Core for FPGA Applications

The objective of this thesis was to develop an 8051 microcontroller soft core in the Verilog hardware description language (HDL). Each functional unit of the 8051 microcontroller was developed as a separate module, and tested for functionality using the open-source VHDL Dalton model as benchmark. These modules were then integrated to operate as concurrent processes in the 8051 soft core. The Verilog 8051 soft core was then synthesized in Quartus® II simulation and synthesis environment (Altera Corp., San Jose, CA, www.altera.com) and yielded the expected behavioral response to test programs written in 8051 assembler residing in the v8051 ROM. The design can operate at speeds up to 41 MHz and used only 16% of the FPGA fabric, thus allowing complex systems to be designed on a single chip. Further research and development can be performed on v8051 to enhance performance and functionality.

Identiferoai:union.ndltd.org:unt.edu/info:ark/67531/metadc11013
Date08 1900
CreatorsRangoonwala, Sakina
ContributorsKougianos, Elias, Mohanty, Saraju P., Hayes, Robert G., Clark, Dave
PublisherUniversity of North Texas
Source SetsUniversity of North Texas
LanguageEnglish
Detected LanguageEnglish
TypeThesis or Dissertation
FormatText
RightsPublic, Copyright, Rangoonwala, Sakina, Copyright is held by the author, unless otherwise noted. All rights reserved.

Page generated in 0.0016 seconds