This thesis work focuses on designing a survivable IP-core network with the minimal investment of spare capacity. A span-oriented spare capacity allocation (SCA) scheme is proposed to satisfy customers' availability requirements in the end-to-end (E2E) sense. The novelty of the proposed SCA scheme is that it meets the E2E availability requirements despite the lack of knowledge of E2E bandwidth by employing protection rings covering all links in the network. Different ring selection methods are presented and also compared from the aspect of network redundancy and LP feasibility which provide more flexibility to the design. The proposed SCA algorithm further minimizes total cost of spare capacity by incorporating partial protection within the proposed architecture. The simulation results show that it can significantly reduce the spare capacity consumption depending on the availability. The proposed SCA scheme also performs better in terms of redundancy than that of two other dominant methods available these days.

This thesis work focuses on designing a survivable IP-core network with the minimal investment of spare capacity. A span-oriented spare capacity allocation (SCA) scheme is proposed to satisfy customers' availability requirements in the end-to-end (E2E) sense. The novelty of the proposed SCA scheme is that it meets the E2E availability requirements despite the lack of knowledge of E2E bandwidth by employing protection rings covering all links in the network. Different ring selection methods are presented and also compared from the aspect of network redundancy and LP feasibility which provide more flexibility to the design. The proposed SCA algorithm further minimizes total cost of spare capacity by incorporating partial protection within the proposed architecture. The simulation results show that it can significantly reduce the spare capacity consumption depending on the availability. The proposed SCA scheme also performs better in terms of redundancy than that of two other dominant methods available these days.

Made available in DSpace on 2015-05-14T12:36:32Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 10319783 bytes, checksum: 6078f95095f94cbeca76282ad5bf6ca7 (MD5) Previous issue date: 2012-08-23 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES / This work is presented as a contribution to the field of design of digital systems integrated on chips (SoCs). Its main focus is to develop and deploy a (new) conceptual framework for the implementation of digital integrated circuits, with a strong emphasis on project management, called LASICProcess. As a natural consequence of the work and serving as a proof of concept, is presented a web application that implements the proposed framework. Among other aspects, it presents a description of the inclusion of a formal project management layer in the digital integrated circuits design flow used by the toolset of open and free software: the Alliance CAD System. The application, which carries the same name as the framework, allows the use of these tools remotely (without the need to install any software on the client side), provides total isolation of the corporate environment with respect to the user interface and was born with a strong vocation to become a powerful resource for collaborative work and even the distance training of human resources for the design of digital integrated circuits. Special care has been devoted to showing that the set of tools used, although being developed and used primarily in academia, provides support to all disciplines addressed and required by commercial and industrial environments for corresponding tasks, as well as to the possibility of (re) configuration of the proposed environment, in order to exchange all or part of the tools ALLIANCE by its equivalent from another provider. / Este trabalho é apresentado como uma contribuição para a área de projetos de sistemas digitais integrados em chips (SoCs). Seu foco principal é desenvolver e implantar um (novo) framework conceitual para a implementação de circuitos integrados digitais, com forte ênfase no gerenciamento de projetos, chamado LASICProcess. Como consequência natural do trabalho e servindo como prova de conceito, é apresentada uma aplicação web que implementa o framework proposto. Entre outros aspectos, ele apresenta a descrição da inclusão de uma camada formal de gestão de projetos no Fluxo de projeto de circuitos integrados utilizado pelo conjunto de ferramentas do Alliance CAD System, de software aberto e livre. A aplicação, que leva o mesmo nome do framework, permite a utilização dessas ferramentas remotamente (sem a necessidade de instalação de nenhum software do lado cliente), provê isolação total do ambiente corporativo com relação à interface do usuário e nasceu com forte vocação para se tornar um potente recurso de trabalho colaborativo e mesmo de formação a distância de recursos humanos para o projeto de circuitos integrados digitais . Especial cuidado foi dedicado à demonstração de que o conjunto de ferramentas utilizado, embora sendo desenvolvido e utilizado principalmente em meio acadêmico, provê suporte a todas as disciplinas contempladas e exigidas pelos ambientes industriais e comerciais para tarefas correspondentes, assim como à possibilidade de (re)configuração do ambiente proposto, para troca total ou parcial das ferramentas ALLIANCE por suas equivalentes de outro provedor.

In der Dissertation werden neue Entwurfsmethoden für Kompaktoren für die Ausgänge von digitalen Schaltungen beschrieben, die die Anzahl der zu testenden Ausgänge drastisch verkleinern und dabei die Testbarkeit der Schaltungen nur wenig oder gar nicht verschlechtern. <br>Der erste Teil der Arbeit behandelt für kombinatorische Schaltungen Methoden, die die Struktur der Schaltungen beim Entwurf der Kompaktoren berücksichtigen. Verschiedene Algorithmen zur Analyse von Schaltungsstrukturen werden zum ersten Mal vorgestellt und untersucht. Die Komplexität der vorgestellten Verfahren zur Erzeugung von Kompaktoren ist linear bezüglich der Anzahl der Gatter in der Schaltung und ist damit auf sehr große Schaltungen anwendbar. <br>Im zweiten Teil wird erstmals ein solches Verfahren für sequentielle Schaltkreise beschrieben. Dieses Verfahren baut im wesentlichen auf das erste auf. <br>Der dritte Teil beschreibt eine Entwurfsmethode, die keine Informationen über die interne Struktur der Schaltung oder über das zugrundeliegende Fehlermodell benötigt. Der Entwurf basiert alleine auf einem vorgegebenen Satz von Testvektoren und die dazugehörenden Testantworten der fehlerfreien Schaltung. Ein nach diesem Verfahren erzeugter Kompaktor maskiert keinen der Fehler, die durch das Testen mit den vorgegebenen Vektoren an den Ausgängen der Schaltung beobachtbar sind. / The objective of this thesis is to provide new space compaction techniques for testing or concurrent checking of digital circuits. In particular, the work focuses on the design of space compactors that achieve high compaction ratio and minimal loss of testability of the circuits. <br>In the first part, the compactors are designed for combinational circuits based on the knowledge of the circuit structure. Several algorithms for analyzing circuit structures are introduced and discussed for the first time. The complexity of each design procedure is linear with respect to the number of gates of the circuit. Thus, the procedures are applicable to large circuits. <br>In the second part, the first structural approach for output compaction for sequential circuits is introduced. Essentially, it enhances the first part. <br>For the approach introduced in the third part it is assumed that the structure of the circuit and the underlying fault model are unknown. The space compaction approach requires only the knowledge of the fault-free test responses for a precomputed test set. The proposed compactor design guarantees zero-aliasing with respect to the precomputed test set.

No description available.

Made available in DSpace on 2014-06-12T16:01:00Z (GMT). No. of bitstreams: 2 arquivo7128_1.pdf: 2072446 bytes, checksum: b6bc5386371d917bd7613b206ac8e92f (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2005 / A demanda cada vez maior por produtos eletronicos e a crescente capacidade de integração dos chips direcionaram a metodologia de projeto de sistemas embarcados para sua completa integração em um único chip ( System-on-Chip, ou SoC). Essa metodologia baseia-se cada vez mais em componentes previamente projetados e verificados (IP-core ) como uma alternativa de disponibilizar os sistemas dentro dos prazos esperados, sem perder o time-to-market do mercado consumidor de eletrônicos. Neste trabalho, é proposto um processo de desenvolvimento de IP-cores baseado em técnicas de engenharia de software chamado ipPROCESS, como um mecanismo de facilitar e promover o desenvolvimento de IP-cores de alta qualidade. Tendo o foco na criação de componentes de qualidade, o ipPROCESS foi definido com base em técnicas de verificação funcional, de modelagem visual da arquitetura, de interface de comunicação e de documentação seguindo os padrões da indústria. O processo foi descrito utilizando o meta-modelo UML denominado SPEM com o objetivo de facilitar e acelerar o seu entendimento, assim como permitir alterações futuras e facilitar o gerenciamento de projetos baseados no processo proposto

The objective of this thesis was to develop an 8051 microcontroller soft core in the Verilog hardware description language (HDL). Each functional unit of the 8051 microcontroller was developed as a separate module, and tested for functionality using the open-source VHDL Dalton model as benchmark. These modules were then integrated to operate as concurrent processes in the 8051 soft core. The Verilog 8051 soft core was then synthesized in Quartus® II simulation and synthesis environment (Altera Corp., San Jose, CA, www.altera.com) and yielded the expected behavioral response to test programs written in 8051 assembler residing in the v8051 ROM. The design can operate at speeds up to 41 MHz and used only 16% of the FPGA fabric, thus allowing complex systems to be designed on a single chip. Further research and development can be performed on v8051 to enhance performance and functionality.

Rapid advances in integration technology have tremendously increased the design complexity of very large scale integrated (VLSI) circuits, necessitating robust optimization techniques in many stages of VLSI design. A genetic algorithm (GA) is a stochastic optimization technique that uses principles derived from the evolutionary process in nature. In this work, genetic algorithms are used to alleviate the hardware design process of VLSI application specific integrated circuits (ASICs) and reconfigurable hardware. VLSI ASIC design suffers from high design complexity and a large number of optimization objectives requiring hierarchical design approaches and multi-objective optimization techniques. The floorplanning stage of the design cycle becomes highly important in hierarchical design methods. In this work, a multi-objective genetic algorithm based floorplanner has been developed with novel crossover operators to address the multi-objective floorplanning problem for VLSI ASICs. The genetic floorplanner achieves significant wirelength savings (>19% on average) with little or no increase in area ( < 3% penalty) over previous floorplanners that perform simultaneous area and wirelength minimization. Hardware implementation of genetic algorithms is gaining importance because of their proven effectiveness as optimization engines for real-time applications. Earlier hardware implementations suffer from major drawbacks such as absence of GA parameter programmability, rigid pre-defined system architecture, and lack of support for multiple fitness functions. A compact IP core that implements a general purpose GA engine has been designed to realize evolvable hardware in field programmable gate array devices. The designed GA core achieved a speedup of around 5.16x over an analogous software implementation. Novel reconfigurable analog architectures have been proposed to realize extreme environment analog electronics. In this work, a digital framework has been developed to realize self reconfigurable analog arrays (SRAA) where genetic algorithms are used to evolve the required analog functionality and compensate performance degradation in extreme environments. The framework supports two methods of compensation, namely, model based lookup and genetic algorithm based compensation and is scalable in terms of the number of fitness evaluation modules. The entire framework has been implemented as a digital ASIC in a leading industrystrength silicon-on-insulator (SOI) technology to obtain high performance and a small form factor.

<p>This thesis aims to investigate a method and tool for emulation of the General Packet Radio Service (GPRS) core network needed as an environment to test the routing functionality. GPRS is the most widely adopted mobile packet data delivery technology in the world. It utilizes an Intranet Protocol (IP)-based core network and involves significant changes to the way the Global System for Mobile communications (GSM) air interface is structured. It also forms the basis of the future structure of mobile network transmission and switching.</p><p>The Serving GPRS Support Node (SGSN) is the most fundamental node in GPRS. Ericsson produces and manages an increasing number of SGSN nodes in the world. One of main functionalities of SGSN node is to forward IP packets according to the destination address in the IP header on IP core network.</p><p>In each new release of SGSN, or when implementation or upgrades have been done on routing application on SGSN, design and test engineers at Ericsson need to emulate the IP core network. This must be done with use of many routers to generate huge amounts of data that can simulate the real world IP core network.</p><p>The major goal of this thesis was to analyze and verifying the use of a suitable and economical solution to emulating IP Core Network of the GPRS system for testing of different functionality of the routing application running in SGSN , instead of building up a physical Core Network with different infrastructure and many routers.</p><p>The method chosen for emulating the IP core network with many routers, and investigated in the thesis, is based on a Cisco simulator called “Dynamips”, which runs many actual Cisco Internetwork Operating Systems (IOS) with many different models of Cisco products in a virtual environment on Windows or Linux platforms. With this simulator, engineers at Ericsson will be able to use this simulator to emulate IP core network easily and efficiently to accomplish system test cases.</p><p>A conclusion of this work is that Dynamips could be used to emulate many complicated IP core network scenarios, with many routers to generate huge amounts of data to simulate the real world IP core network. The emulated system fulfils its purpose for testing of the routing application of SGSN regarding different functionality and characteristics. This is done to ensure and verify that SGSN routing application meets its functional and technical requirements, and also helps to find undiscovered errors as well as helps to ensure that the individual components of routing application on SGSN are working correctly.</p>

This thesis aims to investigate a method and tool for emulation of the General Packet Radio Service (GPRS) core network needed as an environment to test the routing functionality. GPRS is the most widely adopted mobile packet data delivery technology in the world. It utilizes an Intranet Protocol (IP)-based core network and involves significant changes to the way the Global System for Mobile communications (GSM) air interface is structured. It also forms the basis of the future structure of mobile network transmission and switching. The Serving GPRS Support Node (SGSN) is the most fundamental node in GPRS. Ericsson produces and manages an increasing number of SGSN nodes in the world. One of main functionalities of SGSN node is to forward IP packets according to the destination address in the IP header on IP core network. In each new release of SGSN, or when implementation or upgrades have been done on routing application on SGSN, design and test engineers at Ericsson need to emulate the IP core network. This must be done with use of many routers to generate huge amounts of data that can simulate the real world IP core network. The major goal of this thesis was to analyze and verifying the use of a suitable and economical solution to emulating IP Core Network of the GPRS system for testing of different functionality of the routing application running in SGSN , instead of building up a physical Core Network with different infrastructure and many routers. The method chosen for emulating the IP core network with many routers, and investigated in the thesis, is based on a Cisco simulator called “Dynamips”, which runs many actual Cisco Internetwork Operating Systems (IOS) with many different models of Cisco products in a virtual environment on Windows or Linux platforms. With this simulator, engineers at Ericsson will be able to use this simulator to emulate IP core network easily and efficiently to accomplish system test cases. A conclusion of this work is that Dynamips could be used to emulate many complicated IP core network scenarios, with many routers to generate huge amounts of data to simulate the real world IP core network. The emulated system fulfils its purpose for testing of the routing application of SGSN regarding different functionality and characteristics. This is done to ensure and verify that SGSN routing application meets its functional and technical requirements, and also helps to find undiscovered errors as well as helps to ensure that the individual components of routing application on SGSN are working correctly.