Master of Science / Department of Electrical and Computer Engineering / William B. Kuhn / A technique for measuring and characterizing transistor noise is presented. The
primary goal of the measurements is to locate the 1/f noise corner for select transistors in
Silicon-on-Sapphire processes. Additionally, the magnitude of the background channel
noise of each transistor is measured. With this data, integrated circuit (IC) engineers will
have a qualitative and quantitative resource for selecting transistors in designs with low
noise requirements.
During tests, transistor noise behavioral change is investigated over varying channel
lengths, device type (N-type and P-type), threshold voltage, and bias voltage levels.
Noise improvements for increased channel lengths from minimal, 1.0μm, and 4.0μm are
measured. Transistors with medium and high threshold voltages are tested for
comparison of their noise performance. The bias voltages are chosen to represent typical
design values used in practice, with approximately 400 mV overdrive and a drain-to-source
voltage range of 0.5 to 3.0V.
The transistors subjected to tests are custom designed in Peregrine’s 0.5μm (FC)
and 0.25μm (GC) Silicon-on-Sapphire (SOS) processes. In order to allow channel
current noise to dominate over other circuit noise, the transistors have extraordinarily
large aspect ratios (~2500 - 5000).
The transistor noise produced is amplified and measured over a frequency range of
1kHz - 100MHz. This range allows the measurement of each device’s low and high
frequency noise spectrum and resulting noise corner.
| Identifer | oai:union.ndltd.org:KSU/oai:krex.k-state.edu:2097/7137 |
| Date | January 1900 |
| Creators | Albers, Keith Burton |
| Publisher | Kansas State University |
| Source Sets | K-State Research Exchange |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
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