A new optimization technique for SPICE modeling parameters has been developed in this dissertation to increase the accuracy of the circuit simulation. The importance of having accurate circuit simulation models is to prevent the very costly redesign of an Integrated Circuit (IC). This radically new optimization technique utilizes the Taguchi method to improve the fit between measured and simulated I-V curves for GaAs MESFETs. The Taguchi method consists of developing a Signal-to-Noise Ratio (SNR) equation that will find the optimum combination of controllable signal levels in a design or process to make it robust or as insensitive to noise as possible. In this dissertation, the control factors are considered the circuit model curve fitting parameters and the noise is considered the variation in the simulated I-V curves from the measured I-V curves. This is the first known application of the Taguchi method to the optimization of IC curve fitting model parameters. In addition, this method is not technology or device dependent and can be applied to silicon devices as well. Improvements in the accuracy of the simulated I-V curve fit reaching 80% has been achieved between DC test extracted parameters and the Taguchi optimized parameters. Moreover, the computer CPU execution time of the optimization process is 96% less than a commercial optimizer utilizing the Levenberg-Marquardt algorithm (optimizing 31 FETs). This technique does a least square fit on the data comparing measured currents versus simulated currents for various combinations of SPICE parameters. The mean and standard deviation of this least squares fit is incorporated in determining the SNR, providing the best combination of parameters within the evaluated range. Furthermore, the optimum values of the parameters are found without additional simulation by fitting the response curves to a quadratic equation and finding the local maximum. This technique can easily be implemented with any simulator that utilizes simulation modeling parameters extracted from measured DC test data. In addition, two methods are evaluated to obtain the worst case modeling parameters. One method lobks at the correlation coefficients between modeling parameters and the second looks at the actual device parameters that define the +/- 3σ limits of the process. Lastly, an example is given that describes the applicability of the Taguchi methodology in the design of a differential amplifier, that accounts for the effect of offset voltage. / Ph. D.
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/38542 |
| Date | 07 June 2006 |
| Creators | Naber, John F. |
| Contributors | Electrical Engineering, Elshabini-Riad, Aicha A., Nelson, Douglas J., Onishi, S., Riad, S. M., Tront, Joseph G. |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Language | English |
| Detected Language | English |
| Type | Dissertation, Text |
| Format | 7 unnumbered pages, 146 leaves, BTD, application/pdf, application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | OCLC# 29021763, LD5655.V856_1992.N323.pdf |
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