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A genetic parallel programming based logic circuit synthesizer.

Lau, Wai Shing. / Thesis submitted in: November 2006. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 85-94). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Field Programmable Gate Arrays --- p.2 / Chapter 1.2 --- FPGA technology mapping problem --- p.3 / Chapter 1.3 --- Motivations --- p.5 / Chapter 1.4 --- Contributions --- p.6 / Chapter 1.5 --- Thesis Organization --- p.9 / Chapter 2 --- Background Study --- p.11 / Chapter 2.1 --- Deterministic approach to technology mapping problem --- p.11 / Chapter 2.1.1 --- FlowMap --- p.12 / Chapter 2.1.2 --- DAOMap --- p.14 / Chapter 2.2 --- Stochastic approach --- p.15 / Chapter 2.2.1 --- Bio-Inspired Methods for Multi-Level Combinational Logic Circuit Design --- p.15 / Chapter 2.2.2 --- A Survey of Combinational Logic Circuit Representations in stochastic algorithms --- p.17 / Chapter 2.3 --- Genetic Parallel Programming --- p.20 / Chapter 2.3.1 --- Accelerating Phenomenon --- p.22 / Chapter 2.4 --- Chapter Summary --- p.23 / Chapter 3 --- A GPP based Logic Circuit Synthesizer --- p.24 / Chapter 3.1 --- Overall system architecture --- p.25 / Chapter 3.2 --- Multi-Logic-Unit Processor --- p.26 / Chapter 3.3 --- The Genotype of a MLP program --- p.28 / Chapter 3.4 --- The Phenotype of a MLP program --- p.31 / Chapter 3.5 --- The Evolution Engine --- p.33 / Chapter 3.5.1 --- The Dual-Phase Approach --- p.33 / Chapter 3.5.2 --- Genetic operators --- p.35 / Chapter 3.6 --- Chapter Summary --- p.38 / Chapter 4 --- MLP in hardware --- p.39 / Chapter 4.1 --- Motivation --- p.39 / Chapter 4.2 --- Hardware Design and Implementation --- p.40 / Chapter 4.3 --- Experimental Settings --- p.43 / Chapter 4.4 --- Experimental Results and Evaluations --- p.46 / Chapter 4.5 --- Chapter Summary --- p.50 / Chapter 5 --- Feasibility Study of Multi MLPs --- p.51 / Chapter 5.1 --- Motivation --- p.52 / Chapter 5.2 --- Overall Architecture --- p.53 / Chapter 5.3 --- Experimental settings --- p.55 / Chapter 5.4 --- Experimental results and evaluations --- p.59 / Chapter 5.5 --- Chapter Summary --- p.59 / Chapter 6 --- A Hybridized GPPLCS --- p.61 / Chapter 6.1 --- Motivation --- p.62 / Chapter 6.2 --- Overall system architecture --- p.62 / Chapter 6.3 --- Experimental settings --- p.64 / Chapter 6.4 --- Experimental results and evaluations --- p.66 / Chapter 6.5 --- Chapter Summary --- p.70 / Chapter 7 --- A Memetic GPPLCS --- p.71 / Chapter 7.1 --- Motivation --- p.72 / Chapter 7.2 --- Overall system architecture --- p.72 / Chapter 7.3 --- Experimental settings --- p.76 / Chapter 7.4 --- Experimental results and evaluations --- p.77 / Chapter 7.5 --- Chapter Summary --- p.80 / Chapter 8 --- Conclusion --- p.82 / Chapter 8.1 --- Future work --- p.83 / Bibliography --- p.85

Identiferoai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_325887
Date January 2007
ContributorsLau, Wai Shing., Chinese University of Hong Kong Graduate School. Division of Computer Science and Engineering.
Source SetsThe Chinese University of Hong Kong
LanguageEnglish, Chinese
Detected LanguageEnglish
TypeText, bibliography
Formatprint, xvii, 95 leaves : ill. ; 30 cm.
RightsUse of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/)

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