Kan Yeuk Ming. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. / Chapter 1. --- INTRODUCTION --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Objectives --- p.2 / Chapter 1.3 --- Report Organization --- p.3 / Chapter 2. --- RETROSPECT OF NON-MANIFOLD SOLID MODELING --- p.5 / Chapter 2.1 --- Geometric Modeling --- p.5 / Chapter 2.2 --- Euclidean Space and Topological Space --- p.6 / Chapter 2.3 --- Domains of Solid and Non-Manifold Geometric Modeling --- p.8 / Chapter 2.3.1 --- r-set Domain --- p.8 / Chapter 2.3.2 --- Manifold Domain --- p.9 / Chapter 2.3.3 --- Adjacency Form of Topology --- p.11 / Chapter 2.3.4 --- Cell Complex --- p.13 / Chapter 2.4 --- Representation Schemes of Solid and Non-Manifold Geometric Modeling --- p.14 / Chapter 2.4.1 --- Spatial Decomposition --- p.14 / Chapter 2.4.2 --- Constructive Solid Geometry (CSG) --- p.15 / Chapter 2.4.3 --- Boundary Representations (B-rep) --- p.17 / Chapter 2.5 --- Summary --- p.20 / Chapter 3. --- BOOSTING UP THE SPEED OF BOOLEAN OPERATIONS --- p.21 / Chapter 3.1 --- Solid Modeling with Specialized Hardware --- p.22 / Chapter 3.1.1 --- Modeling with a 4x4 Determinant Processor --- p.22 / Chapter 3.1.2 --- Ray Casting Engine --- p.24 / Chapter 3.2 --- Solid Modeling with General Purposed Parallel Computer --- p.25 / Chapter 3.2.1 --- Modeling with Shared Memory Parallel Computer --- p.27 / Chapter 3.2.2 --- Modeling with SIMD Massively Parallel Computer --- p.27 / Chapter 3.2.3 --- Modeling with MIMD Distributed Memory Parallel Computer --- p.30 / Chapter 3.3 --- Summary --- p.33 / Chapter 4. --- OVERVIEW OF DECmpp 12000/Sx/8K --- p.34 / Chapter 4.1 --- System Architecture --- p.34 / Chapter 4.1.1 --- DECmpp Sx Front End --- p.34 / Chapter 4.1.2 --- DECmpp Sx Data Parallel Unit --- p.35 / Chapter 4.1.2.1 --- Array Control Unit --- p.35 / Chapter 4.1.2.2 --- Processor Element Array --- p.35 / Chapter 4.1.2.3 --- Processor Element Communication Mechanism --- p.36 / Chapter 4.2 --- DECmpp Sx Programming Language --- p.37 / Chapter 4.2.1 --- Variable Declarations --- p.37 / Chapter 4.2.2 --- Plural Pointers --- p.38 / Chapter 4.2.3 --- Processor Selection by Conditional Expressions --- p.39 / Chapter 4.2.4 --- Processor Element Communications --- p.39 / Chapter 4.3 --- Summary --- p.40 / Chapter 5. --- ARCHITECTURE OF THE NON-MANIFOLD GEOMETRIC MODELER --- p.41 / Chapter 6. --- SEQUENTIAL MODELER --- p.43 / Chapter 6.1 --- Sequential Half-Wedge structures (SHW) --- p.43 / Chapter 6.2 --- Incremental Topological Operators --- p.51 / Chapter 6.3 --- Sequential Boolean Operations --- p.58 / Chapter 6.3.1 --- Complementing the subtracted model --- p.59 / Chapter 6.3.2 --- Computing intersection of geometric entities --- p.59 / Chapter 6.3.3 --- Construction of sub-faces --- p.53 / Chapter 6.3.4 --- Extraction of resultant topological entities --- p.64 / Chapter 6.4 --- Summary --- p.67 / Chapter 7. --- PARALLEL MODELER --- p.68 / Chapter 7.1 --- Parallel Half-Wedge Structure (PHW) --- p.68 / Chapter 7.1.1 --- Pmodel structure --- p.69 / Chapter 7.1.1.1 --- Phwedge structure --- p.69 / Chapter 7.1.1.2 --- Psurface structure --- p.71 / Chapter 7.1.1.3 --- Pedge structure --- p.72 / Chapter 7.1.2 --- Pmav structure --- p.73 / Chapter 7.2 --- Parallel Boolean Operations --- p.74 / Chapter 7.2.1 --- Complementing the subtracted model --- p.75 / Chapter 7.2.2 --- Intersection computation --- p.79 / Chapter 7.2.2.1 --- Distributing geometric entities --- p.80 / Chapter 7.2.2.2 --- Vertex-Vertex intersection --- p.89 / Chapter 7.2.2.3 --- Vertex-Edge intersection --- p.89 / Chapter 7.2.2.4 --- Edge-Edge intersection --- p.89 / Chapter 7.2.2.5 --- Vertex-Face intersection --- p.90 / Chapter 7.2.2.6 --- Edge-Face intersection --- p.92 / Chapter 7.2.2.7 --- Face-Face intersection --- p.93 / Chapter 7.2.3 --- Constructing sub-faces --- p.98 / Chapter 7.2.4 --- Extraction and construction of resultant topological entities --- p.100 / Chapter 7.3 --- Summary --- p.106 / Chapter 8. --- THE PERFORMANCE OF PARALLEL HALF-WEDGE MODELER --- p.108 / Chapter 8.1 --- The performance of converting sequential to parallel structure --- p.111 / Chapter 8.2 --- The overall performance of parallel Boolean operations --- p.112 / Chapter 8.3 --- The percentage of execution time for individual stages of parallel Boolean operations --- p.119 / Chapter 8.4 --- The effect of inbalance loading to the performance of parallel Boolean operations --- p.121 / Chapter 8.5 --- Summary --- p.125 / Chapter 9. --- CONCLUSIONS AND SUGGESTIONS FOR FURTHER WORK --- p.126 / Chapter 9.1 --- Conclusions --- p.126 / Chapter 9.2 --- Suggestions for further work --- p.127 / APPENDIX / Chapter A. --- SEQUENTIAL HALF-WEDGE STRUCTURE --- p.A-1 / Chapter B. --- COMPUTATION SCHEME IN CHECKING A FACE LOCATING INSIDE THE FACES OF A SOLID --- p.A-3 / Chapter C. --- ALGORITHM IN FINDING A HALF-WEDGE WITH A DIRECTION CLOSEST FROM A REFERENCE HALF-WEDGE --- p.A-5 / Chapter D. --- PARALLEL HALF-WEDGE STRUCTURE --- p.A-7 / REFERENCES --- p.A-10
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_320539 |
| Date | January 1994 |
| Contributors | Kan, Yeuk Ming., Chinese University of Hong Kong Graduate School. Division of Systems Engineering and Engineering Management. |
| Publisher | Chinese University of Hong Kong |
| Source Sets | The Chinese University of Hong Kong |
| Language | English |
| Detected Language | English |
| Type | Text |
| Format | print, iii, 129, [11] leaves : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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