In a conventional hardware design flow, the compilation process to create the physical circuit on the FPGA takes a long time. HMFlow is a design flow that reduces the compilation time by using pre-compiled modules called hard macros. HMFlow uses System Generator to create the designs, which are then converted to hard macros. The hard macro creation process takes a long time and a possible solution is a hard macro generator called XdlCoreGen, which is described in this thesis. XdlCoreGen can quickly create fully mapped and placed hard macros using XDL. XDL is a human readable design format that describes an FPGA and can be manipulated to configure the FPGA. XdlCoreGen also provides a framework to configure a Xilinx Virtex4 FPGA using XDL. In addition to XdlCoreGen, this thesis also describes the FPGA configuration methodology using XDL. This thesis also describes a cache based router, where instead of finding a route, a pre-generated route is used to route the hard macros generated by XdlCoreGen. This thesis also presents test results using XdlCoreGen. However, the main focus of this thesis will be the speed of hard macro generation by XdlCoreGen.
| Identifer | oai:union.ndltd.org:BGMYU2/oai:scholarsarchive.byu.edu:etd-3506 |
| Date | 08 March 2011 |
| Creators | Ghosh, Subhrashankha |
| Publisher | BYU ScholarsArchive |
| Source Sets | Brigham Young University |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Theses and Dissertations |
| Rights | http://lib.byu.edu/about/copyright/ |
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