In a conventional hardware design flow, the compilation process to create the physical circuit on the FPGA takes a long time. HMFlow is a design flow that reduces the compilation time by using pre-compiled modules called hard macros. HMFlow uses System Generator to create the designs, which are then converted to hard macros. The hard macro creation process takes a long time and a possible solution is a hard macro generator called XdlCoreGen, which is described in this thesis. XdlCoreGen can quickly create fully mapped and placed hard macros using XDL. XDL is a human readable design format that describes an FPGA and can be manipulated to configure the FPGA. XdlCoreGen also provides a framework to configure a Xilinx Virtex4 FPGA using XDL. In addition to XdlCoreGen, this thesis also describes the FPGA configuration methodology using XDL. This thesis also describes a cache based router, where instead of finding a route, a pre-generated route is used to route the hard macros generated by XdlCoreGen. This thesis also presents test results using XdlCoreGen. However, the main focus of this thesis will be the speed of hard macro generation by XdlCoreGen.

Field programmable gate arrays (FPGAs) offer an attractive compute platform because of their highly parallel and customizable nature in addition to the potential of being reconfigurable to any almost any desired circuit. However, compilation time (the time it takes to convert user design input into a functional implementation on the FPGA) has been a growing problem and is stifling designer productivity. This dissertation presents a new approach to FPGA compilation that more closely follows the software compilation model than that of the application specific integrated circuit (ASIC). Instead of re-compiling every module in the design for each invocation of the compilation flow, the use of pre-compiled modules that can be "linked" in the final stage of compilation are used. These pre-compiled modules are called hard macros and contain the necessary physical information to ultimately implement a module or building block of a design. By assembling hard macros together, a complete and fully functional implementation can be created within seconds. This dissertation describes the process of creating a rapid compilation flow based on hard macros for Xilinx FPGAs. First, RapidSmith, an open source framework that enabled the creation of custom CAD tools for this work is presented. Second, HMFlow, the hard macro-based rapid compilation flow is described and presented as tuned to compile Xilinx FPGA designs as fast as possible. Finally, several modifications to HMFlow are made such that it produces circuits with clock rates that run at more than 75% of Xilinx-produced implementations while compiling more than 30X faster than the Xilinx tools.