The field programmable gate array (FPGA) is appealing as a computational platform because of its ability to be repurposed for a number of different applications and its relatively low design cost. Traditionally, FPGA vendors provide a set of electronic design automation (EDA) tools to assist customers with the implementation of their designs. These tools are necessarily general purpose, and the resulting tool flow does not provide the user much in the way of customization. Frameworks such as RapidSmith and Torc allow for the creation of custom CAD tools that are able to target actual Xilinx FPGA devices. However, they are built on the Xilinx Design Language (XDL), which was discontinued with the introduction of Xilinx's new tool suite Vivado. Instead, Vivado provides direct access to its data structures through a Tcl interface, as well as EDIF and Xilinx Design Constraint (XDC) files. This thesis discusses Vivado's ability to support a custom CAD tool framework similar to RapidSmith and Torc. It provides a detailed description of the CAD-related aspects of Vivado's Tcl API and shows how its command set can be used to integrate a custom CAD tool framework. This is demonstrated through the introduction of Tincr, a suite of two Tcl-based libraries that each encapsulate a separate method for implementing such a framework. The first is the TincrCAD library, a high-level CAD tool framework built within Vivado's Tcl environment. The second is TincrIO, a set of Tcl commands that comprise a file-based interface into Vivado, similar to XDL. These libraries are offered up as evidence that the Vivado Design Suite can provide a foundation for the implementation of custom CAD tools that operate on Xilinx FPGAs for the foreseeable future.

Field programmable gate arrays (FPGAs) offer an attractive compute platform because of their highly parallel and customizable nature in addition to the potential of being reconfigurable to any almost any desired circuit. However, compilation time (the time it takes to convert user design input into a functional implementation on the FPGA) has been a growing problem and is stifling designer productivity. This dissertation presents a new approach to FPGA compilation that more closely follows the software compilation model than that of the application specific integrated circuit (ASIC). Instead of re-compiling every module in the design for each invocation of the compilation flow, the use of pre-compiled modules that can be "linked" in the final stage of compilation are used. These pre-compiled modules are called hard macros and contain the necessary physical information to ultimately implement a module or building block of a design. By assembling hard macros together, a complete and fully functional implementation can be created within seconds. This dissertation describes the process of creating a rapid compilation flow based on hard macros for Xilinx FPGAs. First, RapidSmith, an open source framework that enabled the creation of custom CAD tools for this work is presented. Second, HMFlow, the hard macro-based rapid compilation flow is described and presented as tuned to compile Xilinx FPGA designs as fast as possible. Finally, several modifications to HMFlow are made such that it produces circuits with clock rates that run at more than 75% of Xilinx-produced implementations while compiling more than 30X faster than the Xilinx tools.