In the recent years, there has been a growing interest in micro- and nano-structured composite systems due to their wide use in microelectronics, optoelectronics, magneto-optical devices, high-density data storage, sensors, biomedical devices, and many other areas. Of particular interest is application in the integrated circuit (IC) industry. Here the need for miniaturization has led to new architectures that combine disparate technologies. This has been achieved through innovations in packaging technologies such as 3D integration for high interconnection density, low power, high data throughput, good signal integrity and reliability, and low cost. One of the key active manufacturing technologies for 3D integration is through silicon vias (TSVs), which involves etching of deep vias in a silicon substrate that are filled with an electrodeposited metal, and subsequent removal of excess metal by chemical mechanical planarization (CMP). Electrodeposition often results in undesired voids in the TSV metal fill as well as a thick overburden layer. These via plating defects can severely degrade interconnect properties and lead to variation in via resistance, electrically open vias, and trapped plating chemicals that present a reliability hazard. Thick overburden layers result in lengthy and expensive CMP processing.
We are proposing a technique that pursues a viable method of depositing a high quality metal inside vias with true bottom-up filling, using an additive-free deposition solution. The mechanism is based on a novel concept of electrochemical oxidation of backside silicon that releases electrons, and subsequent chemical etching of silicon dioxide for regeneration of the surface. Electrons are transported through the bulk silicon to the interface of the via bottom and the deposition solution, where the metal ions accept these electrons and electrodeposit resulting in the bottom-up filling of the large aspect ratio vias. With regions outside the vias covered bydielectric, no metal electrodeposition should occur in these regions, which minimizes the metal CMP step and reduces the overall processing times and costs. Hence, inherent bottom-up filling is financially advantageous because it will eliminate a large portion of the metal overburden and associated planarization costs. Additive-free deposition is preferable from both lower production cost and quality management perspectives since it results in higher reliability of deposited metal. Our new bottom-up technique was initially examined and successfully demonstrated on blanket silicon wafers and shown to supply electrons to provide bottom-up filling advantage of through-hole plating and the depth tailorability of blind vias. In order to understand the driving mechanism and limits of this process, we have also conducted a fundamental study that investigated the effect of various process parameters on the characteristics of deposited Cu and Ni and established correlations between metal filling properties and various electrochemical and solution variables. A copper sulfate solution with temperature of about 65 °C was shown to be suitable for achieving stable and high values of current density that translated to copper deposition rates of ~2.4 μm/min with good deposition uniformity. The importance of backside silicon oxidation and subsequent oxide etching on the kinetics of metal deposition on front side silicon has also been highlighted.
Further, a process model was also developed to simulate the through silicon via copper filling process using conventional and contactless electrodeposition methods with no additives being used in the electrolyte solution. A series of electrochemical measurements were employed and integrated in the development of the comprehensive process simulator. The experimental data not only provided the necessary parameters for the model but also validated the simulation accuracy. From the simulation results, the “pinch-off” effect was observed for the additive-free conventional deposition process, which further causes partial filling and void formation. By contrast, a void-free filling with higher deposition rates was achieved by the use of the contactless technique. Moreover, experimental results of contactless electrodeposition on patterned wafers showed fast rate bottom-up filling (~3.3 μm/min) in vias of 4 μm diameter and 50 μm depth (aspect ratio = 12.5) without void formation and no copper overburden in the regions outside the vias.
Efforts were also made to extend the use of the contactless technique to other applications such as synthesis of porous silicon, which is known to be an excellent material with fascinating physical and chemical properties. We were able to fabricate porous silicon with a morphological gradient using a novel design of the experimental cell. The resulted porous silicon layers show a large distribution in porosity, pore size and depth along the radius of the samples. Symmetrical arrangements were attributed to decreasing current density radially inward on the silicon surface exposed to surfactant containing HF based etchant solution. The formation mechanism as well as morphological properties and their dependence on different process parameters, such as HF concentration, solution pH, surfactant concentration, current density and wafer resistivity, has been investigated in detail. In the presence of surfactants, an increase in the distribution range of porosity, pore diameter and depth was observed by increasing HF concentration or lowering pH of the etchant solution, as the formation of pores was considered to be limited by the etch rates of silicon dioxide. Gradient porous silicon was also found to be successfully formulated both at high and low current densities. Interestingly, the morphological gradient was not developed when dimethyl sulfoxide (instead of surfactants) was used in etchant solution potentially due to limitations in the availability of oxidizing species at the silicon-etchant solution interface.
In the last part of the dissertation, we have discussed the gradient bottom up filling of Cu in porous silicon substrates using the contactless electrochemical method. The radially symmetric current that gradually varied across the radius of the sample area was achieved by utilizing the modified cell design, which resulted in gradient filling in the vias. Effect of different deposition parameters such as applied current density, copper sulfate concentration and etching to deposition area ratio has been examined and discussed. Increasing the current density from 10 to 15 mA/cm2 resulted in bottom up deposition with less sharp gradients. Further, the study on the effect of copper sulfate concentration highlighted the importance of mass transfer in this process, as either bottom-up deposition or gradient filling could not be achieved at lower CuSO4 concentrations (0.1 and 0.25 M). Additionally, the filling gradient of deposited Cu was obtained with etching to deposition area ratio of 1.6 and 2.7, while a more uniform deposition was observed when the ratio was increased to 3.8. This suggested that the gradient filling may only be accomplished within a certain range of the etching to deposition area ratios.
| Identifer | oai:union.ndltd.org:arizona.edu/oai:arizona.openrepository.com:10150/626314 |
| Date | January 2017 |
| Creators | Zhao, Mingrui, Zhao, Mingrui |
| Contributors | Shadman, Farhang, Shadman, Farhang, Raghavan, Srini, Blowers, Paul |
| Publisher | The University of Arizona. |
| Source Sets | University of Arizona |
| Language | en_US |
| Detected Language | English |
| Type | text, Electronic Dissertation |
| Rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. |
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