The goal of more efficiently and more reliably realizing energy conversion in the power electronics industry is pushing the limits of current wire bonding packaging technology. Emerging three-dimensional power packaging techniques have shown their potential to replace wire bonding technology down the road. However, these innovative technologies have not yet been fully understood in terms of thermal and thermo-mechanical performance. Therefore, a comparative evaluation between the thermally induced response in conventional wire bonding (a 2-Dimensional technology) and 3-Dimensional packaging technologies is essential. Thermal and thermo-mechanical analysis using the Finite Element Method (FEM) has been performed to evaluate a three-dimensional power module packaged in a Metal Post Interconnected-Parallel Plate Structure (the MPIPPS), and the result is compared with that of a wire bond module. Under the same single-sided cooling conditions, thermal modeling results show a significantly lower junction temperature of 17oC in the MPIPPS module than that in the wire bond module, due to the more uniform heat flow distribution in the MPIPPS module. The top DBC (direct bonded copper) substrate in the MPIPPS module helps direct the excessive heat generated from IGBT (Insulated Gate Bipolar Transistor) chips to diode chips (which dissipates less heat). The maximum junction temperature is reduced to 108 oC in the MPIPPS module by the implementation of double-sided cooling, which the wire bonding technique can not achieve. Subsequent thermo-mechanical analysis reveals the weak points in both modules during temperature cycling and power cycling. In the wire bond module, temperature cycle results have shown more severe stress and strain than that those of the power cycling conditions in the regions where the wires attach the device emitter pads. In the MPIPPS module, the solder joints exhibit high plastic and creep deformation. Power cycling produces more inelastic deformation at the solder joints between the posts and device, due to local over-heating, which causes more severe high-temperature creep deformation. Using a deformation-based thermal fatigue theory, the solder joint fatigue lives are predicted. Compared with the commercial wire bond module temperature cycle test, the fatigue life of MPIPPS is limited. We conclude that the MPIPPS module is better in thermal management but is thermo-mechanically less reliable than the wire bond module. / Master of Science

In the recent years, there has been a growing interest in micro- and nano-structured composite systems due to their wide use in microelectronics, optoelectronics, magneto-optical devices, high-density data storage, sensors, biomedical devices, and many other areas. Of particular interest is application in the integrated circuit (IC) industry. Here the need for miniaturization has led to new architectures that combine disparate technologies. This has been achieved through innovations in packaging technologies such as 3D integration for high interconnection density, low power, high data throughput, good signal integrity and reliability, and low cost. One of the key active manufacturing technologies for 3D integration is through silicon vias (TSVs), which involves etching of deep vias in a silicon substrate that are filled with an electrodeposited metal, and subsequent removal of excess metal by chemical mechanical planarization (CMP). Electrodeposition often results in undesired voids in the TSV metal fill as well as a thick overburden layer. These via plating defects can severely degrade interconnect properties and lead to variation in via resistance, electrically open vias, and trapped plating chemicals that present a reliability hazard. Thick overburden layers result in lengthy and expensive CMP processing. We are proposing a technique that pursues a viable method of depositing a high quality metal inside vias with true bottom-up filling, using an additive-free deposition solution. The mechanism is based on a novel concept of electrochemical oxidation of backside silicon that releases electrons, and subsequent chemical etching of silicon dioxide for regeneration of the surface. Electrons are transported through the bulk silicon to the interface of the via bottom and the deposition solution, where the metal ions accept these electrons and electrodeposit resulting in the bottom-up filling of the large aspect ratio vias. With regions outside the vias covered bydielectric, no metal electrodeposition should occur in these regions, which minimizes the metal CMP step and reduces the overall processing times and costs. Hence, inherent bottom-up filling is financially advantageous because it will eliminate a large portion of the metal overburden and associated planarization costs. Additive-free deposition is preferable from both lower production cost and quality management perspectives since it results in higher reliability of deposited metal. Our new bottom-up technique was initially examined and successfully demonstrated on blanket silicon wafers and shown to supply electrons to provide bottom-up filling advantage of through-hole plating and the depth tailorability of blind vias. In order to understand the driving mechanism and limits of this process, we have also conducted a fundamental study that investigated the effect of various process parameters on the characteristics of deposited Cu and Ni and established correlations between metal filling properties and various electrochemical and solution variables. A copper sulfate solution with temperature of about 65 °C was shown to be suitable for achieving stable and high values of current density that translated to copper deposition rates of ~2.4 μm/min with good deposition uniformity. The importance of backside silicon oxidation and subsequent oxide etching on the kinetics of metal deposition on front side silicon has also been highlighted. Further, a process model was also developed to simulate the through silicon via copper filling process using conventional and contactless electrodeposition methods with no additives being used in the electrolyte solution. A series of electrochemical measurements were employed and integrated in the development of the comprehensive process simulator. The experimental data not only provided the necessary parameters for the model but also validated the simulation accuracy. From the simulation results, the “pinch-off” effect was observed for the additive-free conventional deposition process, which further causes partial filling and void formation. By contrast, a void-free filling with higher deposition rates was achieved by the use of the contactless technique. Moreover, experimental results of contactless electrodeposition on patterned wafers showed fast rate bottom-up filling (~3.3 μm/min) in vias of 4 μm diameter and 50 μm depth (aspect ratio = 12.5) without void formation and no copper overburden in the regions outside the vias. Efforts were also made to extend the use of the contactless technique to other applications such as synthesis of porous silicon, which is known to be an excellent material with fascinating physical and chemical properties. We were able to fabricate porous silicon with a morphological gradient using a novel design of the experimental cell. The resulted porous silicon layers show a large distribution in porosity, pore size and depth along the radius of the samples. Symmetrical arrangements were attributed to decreasing current density radially inward on the silicon surface exposed to surfactant containing HF based etchant solution. The formation mechanism as well as morphological properties and their dependence on different process parameters, such as HF concentration, solution pH, surfactant concentration, current density and wafer resistivity, has been investigated in detail. In the presence of surfactants, an increase in the distribution range of porosity, pore diameter and depth was observed by increasing HF concentration or lowering pH of the etchant solution, as the formation of pores was considered to be limited by the etch rates of silicon dioxide. Gradient porous silicon was also found to be successfully formulated both at high and low current densities. Interestingly, the morphological gradient was not developed when dimethyl sulfoxide (instead of surfactants) was used in etchant solution potentially due to limitations in the availability of oxidizing species at the silicon-etchant solution interface. In the last part of the dissertation, we have discussed the gradient bottom up filling of Cu in porous silicon substrates using the contactless electrochemical method. The radially symmetric current that gradually varied across the radius of the sample area was achieved by utilizing the modified cell design, which resulted in gradient filling in the vias. Effect of different deposition parameters such as applied current density, copper sulfate concentration and etching to deposition area ratio has been examined and discussed. Increasing the current density from 10 to 15 mA/cm2 resulted in bottom up deposition with less sharp gradients. Further, the study on the effect of copper sulfate concentration highlighted the importance of mass transfer in this process, as either bottom-up deposition or gradient filling could not be achieved at lower CuSO4 concentrations (0.1 and 0.25 M). Additionally, the filling gradient of deposited Cu was obtained with etching to deposition area ratio of 1.6 and 2.7, while a more uniform deposition was observed when the ratio was increased to 3.8. This suggested that the gradient filling may only be accomplished within a certain range of the etching to deposition area ratios.

La miniaturització de la industria microelectrònica és un fet del tot inqüestionables i la tecnologia CMOS no n'és una excepció. En conseqüència la comunitat científica s'ha plantejat dos grans reptes: En primer lloc portar la tecnologia CMOS el més lluny possible ('Beyond CMOS') tot desenvolupant sistemes d'altes prestacions com microprocessadors, micro - nanosistemes o bé sistemes de píxels. I en segon lloc encetar una nova generació electrònica basada en tecnologies totalment diferents dins l'àmbit de les Nanotecnologies. Tots aquests avanços exigeixen una recerca i innovació constant en la resta d'àrees complementaries com són les d'encapsulat. L'encapsulat ha de satisfer bàsicament tres funcions: Interfície elèctrica del sistema amb l'exterior, Proporcionar un suport mecànic al sistema i Proporcionar un camí de dissipació de calor. Per tant, si tenim en compte que la majoria d'aquests dispositius d'altes prestacions demanden un alt nombre d'entrades i sortides, els mòduls multixip (MCMs) i la tecnologia flip chip es presenten com una solució molt interessant per aquests tipus de dispositiu. L'objectiu d'aquesta tesi és la de desenvolupar una tecnologia de mòduls multixip basada en interconnexions flip chip per a la integració de detectors de píxels híbrids, que inclou: 1) El desenvolupament d'una tecnologia de bumping basada en bumps de soldadura Sn/Ag eutèctics dipositats per electrodeposició amb un pitch de 50µm, i 2) El desenvolupament d'una tecnologia de vies d'or en silici que permet interconnectar i apilar xips verticalment (3D packaging) amb un pitch de 100µm. Finalment aquesta alta capacitat d'interconnexió dels encapsulats flip chip ha permès que sistemes de píxels tradicionalment monolítics puguin evolucionar cap a sistemes híbrids més compactes i complexes, i que en aquesta tesi s'ha vist reflectit transferint la tecnologia desenvolupada al camp de la física d'altes energies, en concret implantant el sistema de bump bonding d'un mamògraf digital. Addicionalment s'ha implantat també un dispositiu detector híbrid modular per a la reconstrucció d'imatges 3D en temps real, que ha donat lloc a una patent. / The scaling down of microelectronic's industry is a fact completely unquestionable and the technology CMOS is not an exception. Consequently, the scientific community has considered two great challenges: In first place to bring the technology CMOS the most far away possible ('Beyond CMOS') while developing advanced systems such as microprocessors, micro - nanosystems or pixel systems. On the other hand to begin a new electronic generation based on technologies totally different inside the Nanotechnologies area.All these advances require a research and constant innovation in the rest of complementary areas such as Packaging. Any packaging system has to satisfy three functions in a basic way: Electrical interface of the system with the exterior, to provide a mechanical support to the system and to provide a way of heat dissipation. In order to satisfy the requirements of advanced systems with high number of I/Os, the multichip modules (MCMs) and the flip chip technology are presented as a very interesting solution.The goal of this thesis consist of developing a multichip module technology based on flip chip interconnections for the integration of hybrid pixel detectors, which includes: 1) The development of a bumping technology based on electrodeposited Sn/Ag eutectic solder bumps with a pitch of 50µm, and 2) The development of a technology of gold vias in silicon that allows to interconnect and to stack chips vertically (3D packaging) with a pitch of 100µm.Finally this high capacity of flip chip interconnection has allowed that traditional monolithic pixel systems can evolve towards hybrid systems more compact and complex, and that in this thesis has been reflected transferring the technology developed in the field of the high energies physics, implanting the bump bonding system of a digital mammography system in particular. Additionally also a modular hybrid detecting device (CMOS Image Sensor) has been implanted for the reconstruction of 3D images in real time, which has caused a patent.

La topologie modulaire multiniveaux est une structure d'électronique de puissance construite par la mise en série de sous-modules identiques, composés chacun d'une cellule de commutation et d'un condensateur. Un tel système de conversion pouvant comporter un grand nombre de cellules permet d'augmenter le rendement global et la qualité des signaux en sortie. De plus, il permet d'utiliser des composants basse tension présentant un meilleur comportement dynamique et un rapport qualité-prix bien supérieur aux composants moyenne tension. Il permet également, par rapport aux structures conventionnelles, une grande souplesse pour la conception et la fabrication du fait de son aspect modulaire, tout en s'affranchissant d'un transformateur volumineux et onéreux en entrée. Comparé aux autres types de topologies, avantageuses avec un nombre limité de niveaux, le convertisseur modulaire multiniveaux semble être mieux adapté aux applications en moyenne et haute tensions, qui sont tributaires de l'association des composants de puissance. Néanmoins, pour la variation de vitesse, un certain nombre de défis technologiques ont été mis en évidence, compte tenu du fonctionnement particulier de l'onduleur modulaire multiniveaux et des contraintes imposées par l'opération en très basse fréquence. En le fonctionnement normal, la forme d'onde des courants internes, contrairement aux autres types de topologies, n'est pas symétrique en raison de la distribution du courant direct dans chaque bras. Cela entraîne une disparité significative en termes de dissipation thermique parmi les interrupteurs constituant un sous-module. Avec le choix d'une technologie de packaging 3D, la possibilité de refroidir les puces semi-conductrices en double-face offre une meilleure capacité de refroidissement et une nouvelle perspective de conception des modules pour cette application. Un nouveau concept de report de puces est présenté et un prototype de tel module a été réalisé, modélisé et caractérisé. Il permet d'équilibrer globalement la chaleur dissipée par les puces sur les deux faces du module, problème inhérent à l'emploi de structure 3D. Conjugué à la mutualisation d'un interrupteur par deux puces en parallèle, la nouvelle architecture a aussi pour objectif d'équilibrer le refroidissement double-face dans le temps. En effet, pour les opérations en basse fréquence, les interrupteurs fonctionnent en régime instationnaire avec de forte variation de température, il n'est donc plus possible de compenser les effets thermomécaniques de chaque composant l'un par l'autre, comme en régime stationnaire et avec un positionnement planaire des puces. D'autre part, d'un point de vu systémique, la stratégie de commande et le dimensionnement des condensateurs flottants de l'onduleur modulaire multiniveaux sont deux aspects intimement liés. En effet, les condensateurs flottants sont le siège d'ondulations de tension de très forte amplitude. Cela a pour effet de déstabiliser l'onduleur, voire de provoquer la destruction des composants en atteignant des niveaux de tension trop élevés. Ainsi, des contrôleurs judicieusement conçus permettent de réduire les ondulations indésirables, et a fortiori, d'embarquer des capacités moins importantes dans le système, tant que ces dernières sont inversement proportionnelles à l'ondulation de la tension. Afin d'avoir une compréhension approfondie sur les dynamiques régissant le convertisseur modulaire multiniveaux, un modèle dynamique global basé sur la représentation d'état a été établi. Bien que cette représentation soit limitée à l'harmonique 2 des grandeurs caractéristiques, elle permet une fidèle interprétation du mécanisme de conversion sans passer par des modèles énergétiques bien plus complexes à exploiter, et de proposer des lois de commande montrant leur efficacité notamment autour de la fréquence nominale. Cela a été vérifié sur une maquette de puissance réalisée dans le cadre de cette thèse. / Multilevel modular topology converts energy between two direct and alternative endings. This structure is constructed by the series connection of identical sub-modules, composed of a switching cell and a floating capacitor, and with arm inductors. Such a conversion system may reach a large number of levels increases the overall efficiency and quality of the output signals. In addition, it allows the use of low voltage components with better dynamics and cost effectiveness above the high voltage components. It also allows flexibility in the work of design and manufacture due to its modularity, while avoiding a bulky and expensive input transformer, regarding the conventional technology. Compared with other types of topologies, advantageous with a limited number of levels, the modular multilevel converter seems to be more suited for medium and high voltage applications, which are dependent on the association of power components. However, for variable speed drive application, a certain number of technological challenges have been highlighted, given the specific functional characteristics of the modular multilevel inverter and the constraints imposed by the very low frequency operation. On the one hand, for the normal operation of a multilevel modular converter, the waveform of the internal currents, in contrast to other types of topologies, is not symmetrical due to the distribution of the direct current in each phase leg. This may entail a significant disparity in terms of heat dissipation within the switching devices constituting a sub-module. Therefore, the problem of thermal management of active components is emphasized in the use of a modular multilevel converter. With the choice of a 3D packaging technology, interconnection by bumps, the ability to cool the semiconductor chips through the both sides of a module offers better cooling effects and a new perspective to design the power module for the studied structure. The concept of laying chips on both the two substrates of module without facing each other provides overall balanced dissipation in the space and permit to overcome the unbalanced heat distribution induced by bumps. Combined with the sharing of a switch by two chips in parallel, the proposal of the new architecture for 3D power module also aims to balance the double-sided cooling in the time range. Indeed, for the very low frequency operation, the switches operate in unsteady state where each switch has its own thermal behavior, it is no longer possible to compensate the thermo-mechanical constraints over each component with the help of the others, as in steady state and with a planar chips positioning scheme. On the other hand, from a systemic point of view, the control strategy and the dimensioning of floating capacitors of modular multilevel inverter are two interrelated aspects. Because the floating capacitors, having the role of energy sources, are loaded / unloaded through the modulation period, which causes very high voltage ripples across those capacitors with a very low frequency. This will destabilize the inverter and even provoke the destruction of components by approaching too high voltage levels. Thus, wisely designed controllers reduce unwanted ripples and, furthermore, allow embarking much smaller capacity in the system, as they are inversely proportional to the voltage ripple. In order to have a thorough understanding on the dynamics governing the modular multilevel converter, a comprehensive dynamic model based on state-space representation was established. Although this representation is limited to the second harmonic of characteristic variable, it allows a faithful interpretation of the conversion mechanism without using energy models, more complex to operate, and control laws can also be proposed and their effectiveness around the nominal frequency has been underlined. Concerning the very low frequency operations, another solution has been proposed and is ongoing patent pending.

Les performances, l’encombrement, l’efficacité et la fiabilité des dispositifs sont parmi les enjeux majeurs de l’électronique de puissance. Ils se traduisent sur la conception, la fabrication et le packaging des semiconducteurs. Aujourd’hui, le packaging 3D apporte des réponses concrètes à ces problématiques en regard de l’approche standard (2D). Malgré les excellentes propriétés de ces modules 3D au niveau de la réduction de la signature CEM et du refroidissement, la réalisation, notamment les interconnexions, est complexe. Une approche globale prenant en compte un maximum de paramètres a été développée dans cette thèse. L’ensemble de ce travail s’appuie sur deux propositions que sont la conception couplée entre les composants et le packaging ainsi qu’une fabrication collective à l’échelle de la plaque des modules de puissance. Elles se combinent par la mise en place d’une filière d’étapes technologiques appuyée sur une boite à outils de procédés génériques. Cette approche est concrétisée par la réalisation d’un module de puissance 3D performant et robuste adressant des convertisseurs polyphasés avec des gains aussi bien sur les procédés de fabrication que le module lui-même ainsi que sur le système final.Ce travail offre une nouvelle vision alternative pour l’élaboration des modules électroniques de puissance. Il ouvre également des opportunités pour une fabrication et un packaging plus performants pour les nouveaux semiconducteurs grand gap. / Performances, efficiency and reliability are among the main issues in power electronics. Nowadays, 3D packaging solutions increase standard planar module (2D) performances, for instance EMC. However such integrations are based on complex manufacturing, especially concerning interconnections. Improvements require global and advanced solutions. This work depends on two proposed concepts: a coupled design of the power devices and their associated package and a collective wafer-level process fabrication. A technological offer is proposed based on an innovative power packaging toolbox. Our approach is materialized by the fabrication of a 3D polyphase power module which proved to be more efficient and reliable. The benefits are more precise process manufacturing, lower EMI generation and lower inductive interconnections.As a matter of fact, this work offers a new and advanced technological integration for future power electronics modules, perfectly suitable for the wide bandgap semiconductors.

The development of micro and nano-electromechanical systems (MEMS and NEMS) with entirely new or improved functionalities is typically based on novel or improved designs, materials and fabrication methods. However, today’s micro- and nano-fabrication is restrained by manufacturing paradigms that have been established by the integrated circuit (IC) industry over the past few decades. The exclusive use of IC manufacturing technologies leads to limited material choices, limited design flexibility and consequently to sub-optimal MEMS and NEMS devices. The work presented in this thesis breaks new ground with a multitude of novel approaches for the integration of non-standard materials that enable the fabrication of 3D micro and nanoelectromechanical systems. The objective of this thesis is to highlight methods that make use of non-standard materials with superior characteristics or methods that use standard materials and fabrication techniques in a novel context. The overall goal is to propose suitable and cost-efficient fabrication and integration methods, which can easily be made available to the industry. The first part of the thesis deals with the integration of bulk wire materials. A novel approach for the integration of at least partly ferromagnetic bulk wire materials has been implemented for the fabrication of high aspect ratio through silicon vias. Standard wire bonding technology, a very mature back-end technology, has been adapted for yet another through silicon via fabrication method and applications including liquid and vacuum packaging as well as microactuators based on shape memory alloy wires. As this thesis reveals, wire bonding, as a versatile and highly efficient technology, can be utilized for applications far beyond traditional interconnections in electronics packaging. The second part presents two approaches for the 3D heterogeneous integration based on layer transfer. Highly efficient monocrystalline silicon/ germanium is integrated on wafer-level for the fabrication of uncooled thermal image sensors and monolayer-graphene is integrated on chip-level for the use in diaphragm-based pressure sensors. The last part introduces a novel additive fabrication method for layer-bylayer printing of 3D silicon micro- and nano-structures. This method combines existing technologies, including focused ion beam implantation and chemical vapor deposition of silicon, in order to establish a high-resolution fabrication process that is related to popular 3D printing techniques. / <p>QC 20121207</p>