Semiconductor manufacturing is the workhorse for a wide range of industries. It lies at the heart of consumer electronics, telecommunication equipment and medical devices. Most semiconductor electronics are made from Silicon, and are fabricated using CMOS technology. The versatility of semiconductor electronics stems from the ever-reducing cost of integrating more computing and memory functions on chip. The small cost for adding extra functions has been maintained in the past 50 years through transistor scaling. Transistor scaling focuses on shrinking the size of transistors integrated on chip. This reduction in transistor size, while keeping the overall cost of the chip fixed allowed us to reduce the cost per function with scaling, and is what is celebrated as Moore’s law. Scaling has been working gracefully up to the last decade, where the exponential rise in manufacturing cost and diminishing gains of scaling on device performance reduce its economic benefit. To revive the cost reduction trend, different techniques were proposed such as augmenting CMOS manufacturing with new materials (Beyond-CMOS), 3D integration, and integrating more non-transistor elements on-chip (More than Moore). In this work, we focus on the efficient implementation of several circuit functions using an allotropy of carbon known as graphene. Graphene, a single layer of carbon atoms arranged in a hexagonal lattice, has unique electronic properties that has been taken the solid-state electronics community by a storm since its first experimental conception in 2004. Despite its promising electronic properties, namely the very high charge-carrier mobility and reduced scattering by impurities, graphene circuits has been held back by a plethora of nonidealities and technological roadblocks that hamper its use in traditional transistor-based circuits. In this work, we attempt to leverage the unique physical properties of graphene to implement non von-Neumann neuromorphic computing architectures, low-loss diodes and evaluate the behavior of diffusive-transport graphene couplers. We focus on the the design, fabrication and characterization of graphene devices in the presence of the current performance-limiting technological nonidealities in heterogeneous graphene-CMOS systems. We present the design, fabrication and characterization of all-graphene resistive data converters devices and diodes, discussing their performance and application as building elements of all-graphene brain-inspired computing architectures. We evaluate the performance of graphene couplers operating in the diffusive transport regime, which serve as a method to analyze the cross-coupling between adjacent graphene interconnects. We also discuss the current technological limitations hampering the performance of graphene devices, and the roles of different processing non-idealities on the characteristics of graphene devices.

This paper presents a new technique for the monolithic heterogeneous integration of compound semiconductor devices with silicon integrated circuits, and establishes the theoretical foundation for a key element of the process, tailored magnetic attraction and retention. It is shown how a patterned thin film of hard magnetic material can be used to engineer the attraction between the film and nanopills covered with a soft magnetic material. With a suitable choice of pattern, it is anticipated that it will be possible to achieve complete filling of recesses in the surface of fully-processed integrated circuit wafers, preparatory to subsequent processing to fabricate the nanopills into heterostructure devices integrated monolithically with the pre-existing electronics. / Singapore-MIT Alliance (SMA)

<p>Data acquisition and diagnostics for chemical and biological analytes are critical to medicine, security, and the environment. Miniaturized and portable sensing systems are especially important for medical and environmental diagnostics and monitoring applications. Chip scale integrated planar photonic sensing systems that can combine optical, electrical and fluidic functions are especially attractive to address sensing applications, because of their high sensitivity, compactness, high surface specificity after surface customization, and easy patterning for reagents. The purpose of this dissertation research is to make progress toward a chip scale integrated sensing system that realizes a high functionality optical system integration with a digital microfluidics platform for medical diagnostics and environmental monitoring. </p><p>This thesis describes the details of the design, fabrication, experimental measurement, and theoretical modeling of chip scale optical sensing systems integrated with electrowetting-on-dielectric digital microfluidic systems. Heterogeneous integration, a technology that integrates multiple optical thin film semiconductor devices onto arbitrary host substrates, has been utilized for this thesis. Three different integrated sensing systems were explored and realized. First, an integrated optical sensor based upon the heterogeneous integration of an InGaAs thin film photodetector with a digital microfluidic system was demonstrated. This integrated sensing system detected the chemiluminescent signals generated by a pyrogallol droplet solution mixed with H2O2 delivered by the digital microfluidic system. </p><p>Second, polymer microresonator sensors were explored. Polymer microresonators are useful components for chip scale integrated sensing because they can be integrated in a planar format using standard semiconductor manufacturing technologies. Therefore, as a second step, chip scale optical microdisk/ring sensors integrated with digital microfluidic systems were fabricated and measured. . The response of the microdisk and microring sensing systems to the change index of refraction, due to the glucose solutions in different concentrations presented by the digital microfluidic to the resonator surface, were measured to be 95 nm/RIU and 87nm/RIU, respectively. This is a first step toward chip-scale, low power, fully portable integrated sensing systems. </p><p>Third, a chip scale sensing system, which is composed of a planar integrated optical microdisk resonator and a thin film InGaAs photodetector, integrated with a digital microfluidic system, was fabricated and experimentally characterized. The measured sensitivity of this sensing system was 69 nm/RIU. Estimates of the resonant spectrum for the fabricated systems show good agreement with the theoretical calculations. These three systems yielded results that have led to a better understanding of the design and operation of chip scale optical sensing systems integrated with microfluidics.</p> / Dissertation

This paper describes recent progress in a continuing program to develop and apply RM³ (recess mounting with monolithic metallization) technologies for heterogeneous integration. Particular emphasis is placed on the APB (aligned pillar bonding) and MASA (magnetically assisted statistical assembly) technologies. Next, ongoing research on applications of RM3 integration to produce optoelectronic integrated circuits (OEICs) for optical clock distribution, diffuse optical tomography, and smart pixel arrays are described. Finally, potential new applications of these technologies in intra- and interchip optical signal interconnects, in fluorescent dye detection and imaging for biomedical applications, and in III-V mini-IC integration on Si-CMOS for enhancing off-chip drive capabilities are outlined. / Singapore-MIT Alliance (SMA)

This paper describes recent progress in a continuing program to develop and apply RM³ (recess mounting with monolithic metallization) technologies for heterogeneous integration. Particular emphasis is placed on the applicability of RM³ integration to in-plane geometries for on-chip optical clock and signal distribution and on the suitability of commercially processed IC wafers for use as substrates for rectangular dielectric waveguides. / Singapore-MIT Alliance (SMA)

<p>The integration of planar on-chip light sources is a bottleneck in the implementation of portable planar chip-scale photonic integrated sensing systems, integrated optical interconnects, and optical signal processing systems on platforms such as Silicon (Si) and Si-CMOS integrated circuits. A III/V on-chip laser source integrated onto Si needs to use standard semiconductor fabrication techniques, operate at low power, and enable efficient coupling to other devices on the Si platform.</p><p>In this thesis, thin film strain compensated InGaAs/GaAs single quantum well (SQW) separate confinement heterostructure (SCH) edge emitting lasers (EELs) have been implemented with patterning on both sides of the thin film laser under either growth or host substrate support, with the devices metal/metal bonded to Si and SiO₂/Si substrates. Gain and index guided lasers in various configurations fabricated using standard semiconductor manufacturing processes were simulated, fabricated, and experimentally characterized. Low threshold current densities in the range of 250 A/cm<super>2</super> were achieved. These are the lowest threshold current densities achieved for thin film single quantum well (SQW) lasers integrated on Si reported to date, and also the lowest reported, for thin film lasers operating in the 980 nm wavelength window.</p><p>These thin film EELs were also integrated with photolithographically patterned polymer (SU-8) waveguides on the same SiO₂/Si substrate. Coupling of the laser and waveguide was compared for the cases where an air gap existed between the thin film laser and the waveguide, and in which one facet of the thin film laser was embedded in the waveguide. The laser to waveguide coupling was improved by embedding the laser facet into the waveguide, and eliminating the air gap between the laser and the waveguide. Although the Fresnel reflectivity of the embedded facet was reduced by embedding the facet in the polymer waveguide, leading to a 27.2% increase in threshold current density for 800 &mum long lasers, the slope efficiency of the L-I curves was higher due to preferential power output from the front (now lower reflectivity) facet. In spite of this reduced mirror reflectivity, threshold current densities of 260 A/cm<super>2</super> were achieved for 1000 &mum long lasers. This passively aligned structure eliminates the need for precise placement and tight tolerances typically found in end-fire coupling configurations on separate substrates.</p> / Dissertation

Les systèmes haptiques, ou systèmes de simulation de textures, sont aujourd'hui en plein essor et représentent le prochain challenge pour les appareils mobiles. L'une des solutions les plus prometteuses est celle à base de réduction de friction par vibrations ultrasoniques. L'objectif de cette thèse est de développer une solution haptique répondant au critère d’intégration de la téléphonie mobile en termes d’intégration et de consommation électrique. Plus précisément, il est de proposer une solution à base de couches minces piézoélectriques déposées sur une plaque transparente de la taille d’un écran de smartphone. Après avoir identifié les phénomènes de perception tactile, nous avons établi les spécifications du cahier des charges permettant obtenir un stimulateur haptique. Un modèle théorique de vibration, basé sur la réflexion des ondes de Lamb, nous a permis de déterminer les modes de vibration répondant à ce cahier des charges pour une plaque de la taille d’un smartphone d'écran 5 pouces libre de toutes contraintes. Des transducteurs piézoélectriques en nitrure d’aluminium sont utilisés pour la mise en vibration du système haptique. Déposés sur une face de la plaque, leur position et leur dimensionnement ont été optimisés grâce à des simulations par éléments finis. Le dispositif tactile final sera conçu de façon à laisser un espace central transparent de 4 pouces de diagonal permettant l’ajout d’un écran LCD. Le prototype ainsi déterminé, il est fabriqué grâce à des techniques de dépôt et de gravure en salle blanche. Le dispositif réalisé est caractérisé électriquement et mécaniquement. On détermine alors la puissance nécessaire pour la mise en vibration de la plaque avec des amplitudes correspondant au cahier des charges. Une optimisation de l’électronique de commande permet de réduire la puissance d’actionnement de ce système. Des transducteurs, utilisés en capteurs, sont caractérisés. Ces derniers seront utilisés pour asservir le système dans le cas d’un appui simulant le doigt sur la plaque. / Haptic rendering systems, or textural recreated systems, are nowaday in constant expension and represent the next challenge for the mobile devices. One of the promising solution is based on the friction reduction generated by ultrasonic waves. The aim of this PhD is to develop an haptic rendering solution taking into account the issues of integration into mobile devices in terms of power consumption. More precisely, a solution based on piezoelectric thin films deposited onto a smartphone-sized transparent plate is proposed. Understanding the tactile perception phenomenons, the physical specifications are established in order to obtain an haptic stimulator. A theoretical model based on the Lamb wave reflections determined the vibration modes corresponding to the specifications for a constrain-free 5-inch smartphone size plate.The plate is put into vibration by Aluminum Nitrite thin-film piezoelectric transducers. Processed on one side of the plate, their dimension and position have been optimized thanks to finite element simulations. The final tactile prototype is designed allowing a 4-inch clear centrale space for positioning a futur LCD screen. After this design, the prototype is fabricated with cleanroom processes. The device is then electrically and mechanically characterized. The minimum power necessary to put in vibration the plate is determined, with the minimum specified vibration amplitude. The electronic for the actuation is optimized in order to reduce the power consumption of the system. Transducers, used as sensors, are characterized in order to create a feedback loop. A user case is finally studied to compensate the influence of the finger.

Electronic devices today are an integral part of human life thanks to state-of-the- art complementary metal oxide semiconductor (CMOS) technology. The progress in this area can be attributed to miniaturization driven by Moore’s Law. Further advancements in electronics are under threat from physical limits in dimensional scaling and hence new roadmaps for alternative materials and technologies are chased. Furthermore, the current era of Internet of things (IoT) and Internet of everything (IoE) has broaden the horizon to a plethora of unprecedented applications. The most prominent emerging fields are flexible and stretchable electronics. There has been significant progress in developments of flexible sensors, transistors, and alternative materials, etc. Nonetheless, there remains the unaddressed challenges of matching performance of the status-quo, packaging, interconnects, and lack of pragmatic integration schemes to readily complement existing state-of-the-art technology. In this thesis, a pragmatic heterogeneous integration strategy is presented to obtain high-performance 3D electronic systems using existing CMOS based integrated circuit (IC). Critical challenges addressed during the process are: reliable flexible interconnects, maximum area efficiency, soft-polymeric packaging, and heterogeneous integration compatible with current CMOS technology. First, a modular LEGO approach presents a novel method to obtain flexible electronics in a lock-and-key plug and play manner with reliable interconnects. A process of converting standard rigid IC into flexible LEGO without any performance degradation with a high-yield is shown. For the majority of healthcare and other monitoring applications in IoT, sensory array is used for continuous monitoring and spatiotemporal mapping activities. Here we present ultra-high-density sensory solution (1 million sensors) as an epitome of density and address each of the associated challenges. A generic heterogeneous integration scheme has been presented to obtain physically flexible standalone electronic system using 3D-coin architecture. This 3D-coin architecture hosts sensors on one side, readout circuit and data processing units embedded in the polymer, and the other side is reserved for antenna and energy harvester (photovoltaic). This thin platform (~ 300 μm) has achieved bending radius of 1 mm while maintaining reliable electrical interconnection using through-polymer-via (TPV) and soft-polymeric encapsulation. This coin integration scheme is compatible with existing CMOS technology and suitable for large scale manufacturing. Lastly, a featherlight non-invasive ‘Marine-Skin’ platform to monitor deep-ocean monitoring is presented using the heterogeneous integration scheme. Electrical and mechanical characterization has been done to establish reliability, integrity, robustness, and ruggedness of the processes, sensors, and multisensory flexible system.

No description available.

Over the past four decades, aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistors has resulted in an exponential increase in device density, and thus an exponential increase in computing power. Increasing transistor density also results in increasing total power consumption and thus, necessitates supply voltage scaling in order to maintain low-power device operation. However, with increased supply voltage scaling, transistor drive current is significantly degraded due to the low carrier mobility of Si. To overcome the key challenges of device and voltage scaling required for low-power electronic operation without the degradation of transistor drive current requires the adoption of narrow bandgap channel materials with superior transport properties. However, the use of such materials as bulk substrates remains cost-prohibitive. Thus, another key challenge lies in the heterogeneous integration of high-mobility channel materials on affordable, established Si platform. Germanium (Ge) is an attractive candidate for next-generation low-power devices owing to its high electron and high hole mobility. Recently, AlAs/GaAs epilayers were demonstrated as a potential buffer platform for next-generation Ge-based electronics integrated on Si substrate. This research systematically investigates the structural characteristics of the Ge epitaxial layer heterogeneously integrated on Si using a composite III-V AlAs/GaAs buffer and the electrical characteristics of MOS capacitors (MOS-C's) fabricated on the aforementioned stack. Further passivation techniques and interface engineering is then pursued on MOS-C's fabricated from (100) and (110) crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks, balancing out effective oxide thickness (EOT) and reduction of oxide and interfacial traps in order to ensure a pristine interfacial quality for high-performance electronic applications. Further, work function tuning is demonstrated for the first time on the different crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks using two different gate metals, demonstrating the tunability of threshold voltage, VTH, required for transistor applications. The research demonstrates the feasibility of future high-mobility channel material integration on Si via large bandgap buffer architectures for high-speed, low-power, high-performance CMOS logic applications. / Master of Science