Over the past four decades, aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistors has resulted in an exponential increase in device density, and thus an exponential increase in computing power. Increasing transistor density also results in increasing total power consumption and thus, necessitates supply voltage scaling in order to maintain low-power device operation. However, with increased supply voltage scaling, transistor drive current is significantly degraded due to the low carrier mobility of Si. To overcome the key challenges of device and voltage scaling required for low-power electronic operation without the degradation of transistor drive current requires the adoption of narrow bandgap channel materials with superior transport properties. However, the use of such materials as bulk substrates remains cost-prohibitive. Thus, another key challenge lies in the heterogeneous integration of high-mobility channel materials on affordable, established Si platform. Germanium (Ge) is an attractive candidate for next-generation low-power devices owing to its high electron and high hole mobility. Recently, AlAs/GaAs epilayers were demonstrated as a potential buffer platform for next-generation Ge-based electronics integrated on Si substrate. This research systematically investigates the structural characteristics of the Ge epitaxial layer heterogeneously integrated on Si using a composite III-V AlAs/GaAs buffer and the electrical characteristics of MOS capacitors (MOS-C's) fabricated on the aforementioned stack. Further passivation techniques and interface engineering is then pursued on MOS-C's fabricated from (100) and (110) crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks, balancing out effective oxide thickness (EOT) and reduction of oxide and interfacial traps in order to ensure a pristine interfacial quality for high-performance electronic applications. Further, work function tuning is demonstrated for the first time on the different crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks using two different gate metals, demonstrating the tunability of threshold voltage, VTH, required for transistor applications. The research demonstrates the feasibility of future high-mobility channel material integration on Si via large bandgap buffer architectures for high-speed, low-power, high-performance CMOS logic applications. / Master of Science

Developing high efficiency solar cells for lower manufacturing costs has been a key objective for photovoltaic researchers to drive down the levelized cost of energy for solar power. In this pursuit, III-V compound semiconductor based solar cells have steadily shown performance improvement at approximately 1% (absolute) increase per year, with a recent record efficiency of 46% under concentrator and 32% under AM0. However, the expensive cost has made it challenging for III-V solar cells to compete with the mainstream Silicon (Si) technology. Novel approaches to lower down the cost per watt for III-V solar cells will position them to be among the key contenders in the renewable energy sector. Integration of such high-efficiency III-V multijunction solar cells on significantly cheaper and large area Si substrate has the potential to address the future LCOE roadmaps by unifying the high-efficiency merits of III-V materials with low-cost and abundance of Si. However, the 4% lattice mismatch, thermal mismatch, polar on non-polar epitaxy makes the direct growth of GaAs on Si challenging, rendering the metamorphic cell sensitive to dislocations. The focus of this dissertation is to investigate heterogeneously integrated 1J GaAs solar cells on Si substrate using germanium (Ge) as an intermediate buffer layer that will address mitigation of defects and dislocations between GaAs active cell structure and Ge “virtual” substrate on Si. The all-epitaxial molecular beam epitaxy (MBE)-grown thin (<1 μm) hybrid GaAs/Ge “virtual” buffer approach provided 1J GaAs cell efficiency of ~10% on Si, as compared with cell structures with thick 3 μm GaAs buffers. Solar cell results were further corroborated with material analysis to provide a clear path for the reduction of performance limiting dislocations. The thin “Ge-on-Si” virtual buffer was then investigated comprehensively to understand the impact of the heterostructure on device performance. The growth, structural, morphological, and electrical transport properties of epitaxial thin-film Ge, grown by solid source MBE on Si using a two-step growth process, were investigated. High-resolution x-ray diffraction analysis demonstrated ~0.10% tensile strained Ge epilayer, owing to the thermal expansion coefficient mismatch between Ge and Si, and negligible epilayer lattice tilt due to misfit dislocations at the Ge/Si heterointerface. Micro-Raman spectroscopic analysis further corroborated the strain-state of the Ge thin-film on Si. Cross-sectional transmission electron microscopy revealed the formation of a 90° Lomer dislocation network at the Ge/Si heterointerface, suggesting the rapid and complete relaxation of the Ge epilayer during growth. Atomic force micrographs exhibited smooth surface morphologies with surface roughness < 2 nm. Hall mobility measurements, performed within a temperature range of 77 K to 315 K, and the modelling thereof indicated that ionized impurity scattering limited carrier mobility in the thin Ge epilayer. Additionally, capacitance- and conductance-voltage measurements were performed after fabricating the metal-oxide-semiconductor capacitors (MOS-Cs) in order to determine the effect of epilayer dislocation density on interfacial defect states (Dit), bulk trap density, and the energy distribution of Dit as a function of temperature for electronic device applications. Deep level transient spectroscopy was used to identify the location (within the Ge bandgap) of electrically active trap levels; however, no significant trap levels were detected. Finally, the extracted Dit values were benchmarked against previously reported Dit data for Ge MOS devices, as a function of threading dislocation density within the Ge layer. The results obtained in this work were found to be comparable with other Ge MOS devices integrated on Si via alternative buffer schemes. The understanding gained from this comprehensive study of Ge-on-Si will help optimize the 1J GaAs on Si via thin Ge buffer approach, to enable a future of high efficiency low cost solar cells for terrestrial applications. / Master of Science / The global energy landscape is projected to change remarkably in the coming decades with dwindling carbon based resource reserves and escalating energy demands, necessitating large-scale adoption of cleaner alternatives, such as solar energy. However, for widespread commercial and domestic adoption of photovoltaics, the cost of solar generated electricity must become competitive with non-renewable resources such as oil or coal. Thus, achieving high efficiency solar cells and driving down cell costs are key research objectives of the photovoltaic (PV) community in order to become more self-sufficient in the energy sector. In this pursuit, III-V compound semiconductor-based solar cells have steadily outperformed all other PV technologies, but cost-prohibitive for terrestrial deployment. Si is the undisputed standard in the PV industry; thus, to make a significant step forward in the pursuit of high efficiency solar cells, a promising approach will be to integrate the superior properties of compound semiconductors with the mature technology of Si. This research systematically investigates the integration of high efficiency III-V cells with low cost, abundant Si substrates via a germanium (Ge) layer to unify the performance merits of III-V cells with the cost benefits and superior mechanical and thermal properties of Si. Concurrently, Ge has also emerged as a strong candidate to boost transistor performance at low operating voltages, primarily owing to its superior carrier mobility and ease of integration into mainstream Si process flow. This research further delves into the structural and electrical properties of the Ge on Si structure. Overall, this research demonstrates the feasibility of the use of Ge directly integrated on Si for high efficiency solar cells and low-power electronic devices.

The continued scaling of feature size in silicon (Si)-based complimentary metal-oxide-semiconductor (CMOS) technology has led to a rapid increase in compute power. Resulting from increases in device densities and advances in materials and transistor design, integrated circuit (IC) performance has continued to improve while operational power (VDD) has been substantially reduced. However, as feature sizes approach the atomic length scale, fundamental limitations in switching characteristics (such as subthreshold slope, SS, and OFF-state power dissipation) pose key technical challenges moving forward. Novel material innovations and device architectures, such as group IV and III-V materials and tunnel field-effect transistors (TFETs), have been proposed as solutions for the beyond Si era. TFETs benefit from steep switching characteristics due to the band-to-band tunneling injection of carriers from source to channel. Moreover, the narrow bandgaps of III-V and germanium (Ge) make them attractive material choices for TFETs in order to improve ON-state current and reduce SS. Further, Ge grown on InₓGa₁₋ₓAs experiences epitaxy-induced strain (ε), further reducing the Ge bandgap and improving carrier mobility. Due to these reasons, the ε-Ge/InₓGa₁₋ₓAs system is a promising candidate for future TFET architectures. In addition, the ability to tune the bandgap of Ge via strain engineering makes ε-Ge/InₓGa₁₋ₓAs heterostructures attractive for nanoscale group IV-based photonics, thereby benefitting the monolithic integration of electronics and photonics on Si. This research systematically investigates the material, optical, and heterointerface properties of ε-Ge/InₓGa₁₋ₓAs heterostructures on GaAs and Si substrates. The effect of strain on the heterointerface band alignment is comprehensively studied, demonstrating the ability to modulate the effective tunneling barrier height (Ebeff) and thus the threshold voltage (VT), ON-state current, and SS in future ε-Ge/InₓGa₁₋ₓAs TFETs. Further, band structure engineering via strain modulation is shown to be an effective technique for tuning the emission properties of Ge. Moreover, the ability to heterogeneously integrate these structures on Si is demonstrated for the first time, indicating their viability for the development of next-generation high performance, low-power logic and photonic integrated circuits on Si. / Master of Science

Une technologie d’élaboration de micro et nanosystèmes idéale devrait permettre l’intégration de différents matériaux (magnétiques, piézoélectriques, polymères, etc.) ou structures (composants optiques, mécaniques, optoélectroniques, etc.) de nature fortement hétérogène dans le but d’obtenir des systèmes multifonctionnels complexes éventuellement encapsulés. Un moyen de contourner les différents problèmes d’incompatibilité, liés aux mélanges des technologies de fabrication, est de transférer les différents films de matériaux ou composants d’un substrat donneur, sur lequel ils ont été préalablement élaborés, vers le substrat comportant le système visé Dans cette optique, un procédé de transfert de film à basse température a été développé. Ce procédé repose sur le contrôle de l’adhésion d’un film mince de nickel préformé, à partir d’un substrat dit « donneur », sur une couche à adhésion contrôlée de nature carbonée ou fluorocarbonée. La libération mécanique du film, sur un substrat dit « cible », est assurée par une soudure adhésive via des cordons de scellement en BCB. Grâce à sa facilité de mise en œuvre et aux faibles températures requises pour le scellement des substrats, ce procédé a permis de transférer des microstructures en nickel sur des substrats de silicium, de verre ainsi que sur des substrats Kapton souples. L’emploi d’une soudure BCB assure l’isolation thermique et électrique des microstructures sur le substrat cible. La versatilité du procédé a été prouvée par l’empilement de microstructures suspendues et par le transfert de divers matériaux. Ce procédé est très prometteur pour de nombreuses applications et apporte de nouvelles perspectives quant à l’intégration hétérogène 3D de micro et nanosystèmes. / Nowadays, micro and nano systems fabrication technologies should allow the integration of any passive or active materials (magnetic, piezoelectric, polymers, etc.) in various forms (films, micro/nanostructures, etc.) to build and/or package highly integrated multi-functional systems. A generic technology able to solve incompatibility issues related to the mixing of different technologies is pattern or device transfer by wafer bonding from a donor wafer to the target substrate. Ideally, such a process should be versatile, low cost, selective and over all should involve minimum interaction and processing steps on the target wafer. From this perspective, a low cost and low temperature MEMS transfer process has been developed. The process is based on adhesion control of molded electroplated Ni microstructures on the donor wafer by using plasma deposited fluorocarbon films and sputtered carbon films (for high temperature materials). Adhesive bonding of the microstructures on the target wafer using BCB sealing enables mechanical tearing off from the donor wafer. This proposed process has allowed us to realize various Ni patterns on Si, Pyrex glass wafers and Kapton foils. Furthermore, BCB sealing leads to freestanding microstructures which are thermally and electrically isolated from the target substrate. Thanks to multiple transfers, Ni stacked microstructures have been achieved. The transfer of various materials has been demonstrated for simple and complex structures. This transfer process is very promising for numerous applications and brings new perspectives towards 3D microfabrication and heterogeneous integration of MEMS/NEMS.

A fast and efficient hierarchical optimization engine was developed to benchmark and optimize various emerging device and interconnect technologies and system-level innovations at the early design stage. As the semiconductor industry approaches sub-20nm technology nodes, both devices and interconnects are facing severe physical challenges. Many novel device and interconnect concepts and system integration techniques are proposed in the past decade to reinforce or even replace the conventional Si CMOS technology and Cu interconnects. To efficiently benchmark and optimize these emerging technologies, a validated system-level design methodology is developed based on the compact models from all hierarchies, starting from the bottom material-level, to the device- and interconnect-level, and to the top system-level models. Multiple design parameters across all hierarchies are co-optimized simultaneously to maximize the overall chip throughput instead of just the intrinsic delay or energy dissipation of the device or interconnect itself. This optimization is performed under various constraints such as the power dissipation, maximum temperature, die size area, power delivery noise, and yield. For the device benchmarking, novel graphen PN junction devices and InAs nanowire FETs are investigated for both high-performance and low-power applications. For the interconnect benchmarking, a novel local interconnect structure and hybrid Al-Cu interconnect architecture are proposed, and emerging multi-layer graphene interconnects are also investigated, and compared with the conventional Cu interconnects. For the system-level analyses, the benefits of the systems implemented with 3D integration and heterogeneous integration are analyzed. In addition, the impact of the power delivery noise and process variation for both devices and interconnects are quantified on the overall chip throughput.

L’intégration du GaAs sur Si est un des défis majeurs des 40 dernières années puisqu’elle permettrait de combiner les nombreux avantages du Si, dont notamment son bas coût, avec les propriétés de haute mobilité et de gap direct du GaAs. Les cellules photovoltaïques multi-jonctions à base de matériau III-V permettent d’obtenir les plus hauts rendements de conversion photovoltaïque. Cependant, leur coût de fabrication élevé est un aspect limitatif de leur utilisation. Nous nous sommes intéressés ici à une étude préliminaire visant à réaliser leur intégration sur substrat Si. In fine, l’objectif sera la réalisation de cellules tandems GaAs/Si et GaAs/Ge sur substrat Si. L’intégration du GaAs et du Ge sur Si conduit cependant à la formation de dislocations et de fissures du fait de leurs désaccords de maille et de leurs différences de coefficient d’expansion thermique respectifs. De plus, du fait de la différence de polarité entre le GaAs et le Si, cette intégration conduit également à la formation de domaine d’anti-phase. Nous présentons dans cette étude un procédé d’intégration permettant à la fois l’élimination de ces défauts et le passage du courant entre le matériau épitaxié et le Si. Ce procédé est basé sur l’utilisation d’ouvertures de tailles nanométriques dans une silice fine, qui nous permet ainsi de réaliser la croissance du GaAs sur Si sous forme de cristaux, par épitaxie latérale à partir de nano-germes de GaAs ou de Ge. Pour ce faire, nous utilisons l’épitaxie par jet chimique sans gaz vecteur qui est une technique de croissance permettant une bonne sélectivité. La croissance sera tout d’abord étudiée dans des ouvertures aléatoires, facilement réalisées in-situ sous ultravide, puis dans des ouvertures localisées de tailles fixées. Ces dernières sont obtenues suite à une procédure longue et complexe qui repose sur des étapes de nettoyage chimique, d’enrésinement, de lithographie électronique, de développement et de gravure ionique réactive. Nous présenterons les résultats de la croissance directe de cristaux de GaAs dans les ouvertures sur Si (001) et Si (111), et également à partir de nano-germes de Ge. Ce procédé d’intégration a permis l’élimination des trois types de défauts précédemment indiqués, et nous avons obtenu de très bons résultats notamment lors de l’intégration dans les ouvertures localisées sur Si (111). Nous verrons que la morphologie des nano-germes de Ge peut toutefois être problématique lors de la reprise d’épitaxie du GaAs. La possibilité de passage du courant par effet tunnel à travers la silice fine sera ensuite vérifiée et le dopage des cristaux de GaAs avec du Si sera également présenté. / GaAs on Si integration is one of the major challenges of the last 40 years as it would allow to combine Si advantages, like its low cost, with GaAs high mobility and direct bandgap. Multi-junction photovoltaic cells based on III-V materials have the highest photovoltaic conversion efficiencies. However, their high manufacturing cost is a limiting aspect of their use. This is why we have made a preliminary study aiming at realizing their integration on Si substrate. In fine, the objective will be the realization of tandem solar cells made of GaAs/Si and GaAs/Ge on Si substrate. However, GaAs and Ge integrations on Si lead to dislocations and cracks formations because of their respective differences of lattices parameters and thermal expansion coefficients. Moreover, because of the difference of polarity between GaAs and Si, this integration also leads to anti-phase domain formation. We present in this study an integration process allowing both these defects elimination and current passage between the epitaxial material and Si. This process is based on the use of nanoscale openings in a thin silica, which allows us to carry out GaAs crystals growth on Si by lateral epitaxy from GaAs or Ge nano-seeds. To do this, we use chemical beam epitaxy which is a growth technique allowing good selectivity. Firstly, the growth will be studied inside randomly dispersed openings, which are easily made in situ under ultra-high vacuum, and then inside localized openings with fixed sizes. These are obtained after a long and complex procedure including chemical cleaning, resist spin-coating, electronic lithography, development and reactive ion etching. We will present GaAs crystals direct growth inside openings on Si (001) and (111), and also from Ge nano-seeds. This integration process allowed the elimination of the three types of defects previously mentioned, and we have obtained very good results especially for the integration inside localized openings on Si (111). We will see that Ge nano-seeds morphology can however be problematic during the GaAs lateral epitaxy. In addition, the current passage by tunnel effect through the thin silica will be verified and the GaAs crystals doping with Si will also be presented.

Achieving high efficiency solar cells and concurrently driving down the cell cost has been among the key objectives for photovoltaic researchers to attain a lower levelized cost of energy (LCOE). While the performance of silicon (Si) based solar cells have almost saturated at an efficiency of ~25%, III-V compound semiconductor based solar cells have steadily shown performance improvement at approximately 1% (absolute) increase per year, with a recent record efficiency of 46%. However, the expensive cost has made it challenging for the high efficiency III-V solar cells to compete with the mainstream Si technology. Novel approaches to lower down the cost per watt for III-V solar cells will position them to be among the key contenders in the renewable energy sector. Integration of such high-efficiency III-V multijunction solar cells on significantly cheaper and large area Si substrate has the potential to address the future LCOE roadmaps by unifying the high-efficiency merits of III-V materials with low-cost and abundance of Si. However, the 4% lattice mismatch, thermal mismatch polar-on-nonpolar epitaxy makes the direct growth of GaAs on Si challenging, rendering the metamorphic cell sensitive to dislocations. The focus of this dissertation is to systematically investigate heterogeneously integrated III-V multijunction solar cells on Si substrate. Utilizing a combination of comprehensive solar cell modeling and experimental techniques, we seek to better understand the material properties and correlate them to improve the device performance, with simulation providing a very valuable feedback loop. Key technical design considerations and optimal performance projections are discussed for integrating metamorphic III-V multijunction solar cells on Si substrates for 1-sun and concentrated photovoltaics. Key factors limiting the “GaAs-on-Si” cell performance are identified, and novel approaches focused on minimizing threading dislocation density are discussed. Finally, we discuss a novel epitaxial growth path utilizing high-quality and thin epitaxial Ge layers directly grown on Si substrate to create virtual “Ge-on-Si” substrate for III-V-on-Si multijunction photovoltaics. With the plummeting price of Si solar cells accompanied with the tremendous headroom available for improving the III-V solar cell efficiencies, the future prospects for successful integration of III-V solar cell technology with Si substrate looks very promising to unlock an era of next generation of high-efficiency and low-cost photovoltaics. / Ph. D.

Les systèmes optomécaniques, dans lesquels les vibrations d'un résonateur mécanique sont couplées à un rayonnement électromagnétique, ont permis l'examen de multiples nouveaux effets physiques. Afin d'exploiter pleinement ces phénomènes dans des circuits réalistes et d'obtenir différentes fonctionnalités sur une seule puce, l'intégration des résonateurs optomécaniques est obligatoire. Ici nous proposons une nouvelle approche pour la réalisation de systèmes intégrés et hétérogènes comportant des cavités à cristaux photoniques bidimensionnels au-dessus de guides d'ondes en silicium-sur-isolant. La réponse optomécanique de ces dispositifs est étudiée et atteste d'un couplage optomécanique impliquant à la fois les mécanismes dispersifs et dissipatifs. En contrôlant le couplage optique entre le guide d'onde intégré et le cristal photonique, nous avons pu varier et comprendre la contribution relative de ces couplages. Cette plateforme évolutive permet un contrôle sans précédent sur les mécanismes de couplage optomécanique, avec un avantage potentiel dans des expériences de refroidissement et pour le développement de circuits optomécaniques multi-éléments pour des applications tels que le traitement du signal par effets optomécaniques. / Optomechanical systems, in which the vibrations of a mechanical resonator are coupled to an electromagnetic radiation, have permitted the investigation of a wealth of novel physical effects. To fully exploit these phenomena in realistic circuits and to achieve different functionalities on a single chip, the integration of optomechanical resonators is mandatory. Here, we propose a novel approach to heterogeneously integrated arrays of two-dimensional photonic crystal defect cavities on top of silicon-on-insulator waveguides. The optomechanical response of these devices is investigated and evidences an optomechanical coupling involving both dispersive and dissipative mechanisms. By controlling optical coupling between the waveguide and the photonic crystal, we were able to vary and understand the relative strength of these couplings. This scalable platform allows for unprecedented control on the optomechanical coupling mechanisms, with a potential benefit in cooling experiments, and for the development of multi-element optomechanical circuits in the frame of optomechanically-driven signal-processing applications.

Cette thèse fait partie des efforts de recherche pour étudier l’intégration hétérogène sur le substrat souple des nœuds de communicants pour les réseaux de capteurs sans fil dans la bande à 60GHz. Le System in Package (SiP) devrait avoir une consommation d'énergie très faible et être faible coût pour répondre aux exigences des applications telles que la Surveillance de Santé de Structure (Structure Health Monitoring - SHM en anglais) dans le domaine aéronautique par exemple. Chaque nœud est composé des nano-capteurs, des transceivers et des antennes d’émission et de réception. Les nanotechnologies ont permis le développement de nano-capteurs ultra-sensibles à base de nanoparticules. Les transceivers deviennent de plus en plus miniaturisés et donc permettre la possibilité de les reporter sur le substrat flexible. Les antennes peuvent être intégrés sur le substrat flexible avec les nano-capteurs développés et émetteurs miniaturisés, ce qui est l'approche très innovante. Dans cette thèse, nous présenterons les procédés technologiques adaptés pour réaliser les différents circuits passifs (résonateurs, antennes, rectennas, etc…) sur le substrat souple en utilisant la photolithographie conventionnelle. La technique de la puce retournée a été choisie pour l’intégration des transceivers à 60 GHz, la formation des bosses d’interconnexion en or directement sur le substrat souple par les dépôts électrolytiques est présentée ici pour la première fois. La concordance entre les mesures expérimentales et les simulations numériques démontre la fiabilité et la reproductibilité des procédés choisis. De plus, pour une application à volume élevé comme les réseaux de capteurs sans fil, le coût de fabrication par nœud peut être considérablement réduit, et devient comparable avec l’impression jet d'encre qui est un procédé à faible coût. / This thesis is part of research effort to develop a 3D heterogeneous integration of wireless sensor node on flexible substrate for the unlicensed 60GHz band. The System in Package (SiP) should have a very low power consumption and very low cost to meet the requirements of applications like Wireless Sensor Networks (WSNs) for Structure Health Monitoring (SHM). Using a flexible substrate for wireless sensor node integration can offer the advantage of being localized in areas with access difficulty especially in non-planar area. Each node is composed of nano-sensors, transceivers and TX/RX antenna. Nanotechnologies made it possible the development of ultra-sensitive nano-sensors based on nanoparticles deposition. Transceivers become more and more miniaturized and hence enable the possibility of postpone them onto flexible substrate. The antennas can be integrated on the flexible substrate along with the developed nano-sensors and miniaturized transceivers, which is the very innovative approach. In this work, we propose customized photolithography processes to manufacture the passive element circuits (resonators, antennas, rectennas, etc…) on flexible substrate. The technique of flip-chip was used for the integration of 60 GHz transceivers, a novel technique to form Au interconnection bump directly onto the flexible substrate by using electrodeposition process is also presented here for the first time. The concordance between the simulations and the measurements is observed, which proves the reliability and reproducibility of such process technique. Furthermore, for a high-volume application like the node deployment of WSNs, wafer cost reductions can significantly lower the total cost per node and became comparable to a low-cost inkjet printing process.

Due to the changing scope of data management towards the management of heterogeneous and distributed systems and applications, integration processes gain in importance. This is particularly true for those processes used as abstractions of workflow-based integration tasks; these are widely applied in practice. In such scenarios, a typical IT infrastructure comprises multiple integration systems with overlapping functionalities. The major problems in this area are high development effort, low portability and inefficiency. Therefore, in this paper, we introduce the vision of invisible deployment that addresses the virtualization of multiple, heterogeneous, physical integration systems into a single logical integration system. This vision comprises several challenging issues in the fields of deployment aspects as well as runtime aspects. Here, we describe those challenges, discuss possible solutions and present a detailed system architecture for that approach. As a result, the development effort can be reduced and the portability as well as the performance can be improved significantly.