Counterfeit Integrated Circuits (ICs) are previously used ICs that are resold as new. They have become a serious problem in modern electronic devices. They cause lower performance, reduced life span and even catastrophic failure of systems and platforms. To prevent counterfeiting and the associated revenue loss, there is need for non-invasive and inexpensive techniques to establish the authenticity of devices. We describe a technique to detect a counterfeit IC that does not have any special anti-counterfeiting mechanisms built-in prior to deployment. Our detection criterion is based on measuring path delays. The experiments show that a single path delay cannot directly reveal the age, as it is also greatly influenced by process variation and this could result in large error in classifying ICs as authentic or counterfeit. �Instead, we establish that the relationship between the delays of two or more paths is a great indicator for the age of device. The idea is to project ICs from different age groups onto the space of the path delays and train a trusted reference hyper-surface for each age group. Ideally, the hyper-surfaces do not overlap. In this way, an IC under test can be assigned to one hyper-surface based on the distance of its footprint with respect to these hyper-surfaces, thus predicting its age. In our simulations, we observe over 97% correct prediction of identifying an aged IC from a new IC. / Master of Science

Large dense structures like DRAMs (Dynamic Random Access Memory) are particularly susceptible to process variation, which can lead to variable latencies in different memory arrays. However, very little work exists on variation studies in DRAMs. This is due to the fact that DRAMs were traditionally placed off-chip and their latency changes due to process variation did not impact the overall processor performance. However, emerging technology trends like three-dimensional integration, use of sophisticated memory controllers, and continued scaling of technology node, substantially reduce DRAM access latency. Hence, future technology nodes will see widespread adoption of embedded DRAMs. This makes process variation a critical upcoming challenge in DRAMs that must be addressed in current and forthcoming technology generations. In this paper, techniques for modeling the effect of random, as well as spatial variation, in large DRAM array structures are presented. Sensitivity-based gate level process variation models combined with statistical timing analysis are used to estimate the impact of process variation on the DRAM performance and leakage power. A simulated annealing-based Vth assignment algorithm using adaptive body biasing is proposed in this thesis to improve the yield of DRAM structures. By applying the algorithm on a 1GB DRAM array, an average of 14.66% improvement in the DRAM yield is obtained.

Thesis (M.Sc.Eng.) / As semiconductor technology has been scaled down, increased variation in process parameters results in the variation of key device parameters, which will change the performance and operation of the integrated circuit. This MSEE thesis involves the study of the effects of process variation on the behavior of an 8-GHz clock generator (synthesizer) designed in the 0.13μm IBM 8HP BiCMOS technology, and the recommendation of changes that could be mader to the design that would make it more tolerant to process variation. The first part of this MS research project has involved the design of the phase-locked loop (PLL). The PLL contains a differential VCO (voltage-controller oscillator), a TPSC-DFF (True Single-Phase Clock D-Flip Flop) based 2/3/4 frequency divider, a phase frequency detector, a charge pump, a low-pass filter, a logic control circuit and several buffers. since 8 GHz is a fairly high frequency for a clock generator in a 0.13μm technology and since high frequency circuit layouts inevitable degenerate the circuit performance, the frequency in the design part must necessarily be even higher than the specification. Therefore, this work combines the use of the known fastest architecture in every individual part. After completing the design of the synthesizer, it was simulated in Cadence, first with schematic-based models, using the IBM 8HP design kit, and was studies with statistical distributions utilized for key device parameters, as provided by the design kit. the layout of the circuit was completed and the simulations were redone using extracted models, based on the layouts, with the statistical parameter distributions included. According to Monte Carlo distribution simulation results, the most sensitive parameters were identified and analyzed. Based on those results, changes to the circuit have been proposed and studied, such as changes in device W and L, number of gate fingers nf, use of device multiplicity m, and/or changes to the basic circuit architecture to attempt to minimize the effects of process variation behavior functionality of the circuit.

In nanometer technologies, process variation control and low power have emerged as the first order design goal after high performance. Process variations cause high variability in performance and power consumption of an IC, which affects the overall yield. Short channel effects (SCEs) deteriorate the MOSFET performance and lead to higher leakage power. Double gate devices suppress SCEs and are potential candidates for replacing Bulk technology in nanometer nodes. Threshold voltage control in planar asymmetric double gate transistor (IGFET) using a fourth terminal provides an effective means of combating process variations and low power design. In this thesis, using various case studies, we analyzed the suitability of IGFET for variation control and low power design. We also performed an extensive comparison between IGFET and Bulk for reducing variability, improving yield and leakage power reduction using power gating. We also proposed a new circuit topology for IGFET, which on average shows 33.8 percent lower leakage and 34.9 percent lower area at the cost of 2.8 percent increase in total active mode power, for basic logic gates. Finally, we showed a technique for reducing leakage of minimum sized devices designed using new circuit topology for IGFET.

While transistor size continues to shrink every technology generation increasing the amount of transistors on a die, the reduction in energy consumption is less significant. Furthermore, newer technologies induce fabrication challenges resulting in uncertainties in transistor and wire properties. Therefore to ensure correctness, design margins are introduced resulting in significantly sub-optimal energy efficiency. While increasing parallelism and the use of gating methods contribute to energy consumption reduction, ultimately, more radical changes to the architecture and better integration of architectural and circuit techniques will be necessary. This dissertation explores one such approach, combining a highly-efficient massively-parallel processor architecture with a design methodology that reduces energy by trimming design margins. Using a massively-parallel GPU-like (graphics processing unit) base- line architecture, we discuss the different components of process variation and design microarchitectural approaches supporting efficient margins reduction. We evaluate our design using a cycle-based GPU simulator, describe the conditions where efficiency improvements can be obtained, and explore the benefits of decoupling across a wide range of parameters. We architect a test-chip that was fabricated and show these mechanisms to work. We also discuss why previously developed related approaches fall short when process variation is very large, such as in low-voltage operation or as expected for future VLSI technology. We therefore develop and evaluate a new approach specifically for high-variation scenarios. To summarize, in this work, we address the emerging challenges of modern massively parallel architectures including energy efficient, reliable operation and high process variation. We believe that the results of this work are essential for breaking through the energy wall, continuing to improve the efficiency of future generations of the massively parallel architectures. / text

Sense amplifiers are important circuit components of a dynamic random access memory (DRAM), which forms the main memory of digital computers. The ability of the sense amplifier to detect and amplify voltage signals to correctly interpret data in DRAM cells cannot be understated. The sense amplifier plays a significant role in the overall speed of the DRAM. Sense amplifiers require matched transistors for optimal performance. Hence, the effects of mismatch through process variations must be minimized. This thesis presents a research which leads to optimal nanoscale CMOS sense amplifiers by incorporating the effects of process variation early in the design process. The effects of process variation on the performance of a standard voltage sense amplifier, which is used in conventional DRAMs, is studied. Parametric analysis is performed through circuit simulations to investigate which parameters have the most impact on the performance of the sense amplifier. The figures-of-merit (FoMs) used to characterize the circuit are the precharge time, power dissipation, sense delay and sense margin. Statistical analysis is also performed to study the impact of process variations on each FoM. By analyzing the results from the statistical study, a method is presented to select parameter values that minimize the effects of process variation. A design flow algorithm incorporating dual oxide and dual threshold voltage based techniques is used to optimize the FoMs for the sense amplifier. Experimental results prove that the proposed approach improves precharge time by 83.9%, sense delay by 80.2% sense margin by 61.9%, and power dissipation by 13.1%.

Trustworthy authentication of an object is of extreme importance for secure protocols. Traditional methods of storing the identity of an object using non-volatile memory is insecure. Novel chip-identifiers called Silicon Physical Unclonable Functions (PUFs) extract the random process characteristics of an Integrated Circuit to establish the identity. Though such types of IC identifiers are difficult to clone and provide a secure, yet an area and power efficient authentication mechanism, they suffer from instability due to variations in environmental conditions and noise. The decreased stability imposes a penalty on the area of the PUF circuit and the corresponding error correcting hardware, when trying to generate error-free bits using a PUF. In this thesis, we propose techniques to improve the popular delay-based PUF architectures holistically, with a focus on its stability. In the first part, we investigate the effectiveness of circuit-level optimizations of the delay based PUF architectures. We show that PUFs which operate in the subthreshold region, where the transistor supply voltage is maintained below the threshold voltage of CMOS, are inherently more stable than PUFs operating at nominal voltage because of the increased difference in characteristics of transistors at this region. Also, we show that subthreshold PUF enjoys higher energy and area efficiency. In the second part of the thesis, we propose a feedback-based supply voltage control mechanism and a corresponding architecture to improve the stability of delay-based PUFs against variations in temperature. / Master of Science

A Physical Unclonable Function (PUF) has shown a lot of promise to solve many security issues due to its ability to generate a random yet chip-unique secret in the form of an identifier or a key while resisting cloning attempts as well as physical tampering. It is a hardware-based challenge-response function which maps its responses to its challenges exploiting complex statistical variation in the logic and interconnect inside integrated circuits (ICs). An efficient PUF should generate a key that varies randomly from one chip to another. At the same time, it should reliably reproduce a key from a chip every time the key is requested from that chip. Moreover, a PUF should be robust to thwart any attack that aims to reveal its key. Designing an efficient PUF having all these qualities with a low cost is challenging. Furthermore, the efficiency of a PUF needs to be validated by characterizing it over a group of chips. This is because a PUF circuit is supposed to be instantiated in several chips, and whether it can produce a chip-unique identifier/key or not cannot be validated using a single chip. The main goal of this research is to propose a systematic approach to build a random, reliable, and robust PUF incurring minimal cost. With this objective, we first formulate a novel PUF system model that uncouples PUF measurement from PUF identifier formation. The proposed model divides PUF operation into three separate but related components. We show that the three PUF quality factors, randomness, reliability, and robustness, can be improved at each component of the system model resulting in an overall improvement of a PUF. We proposed three PUF enhancement techniques using the system model in this research. The proposed techniques showed significant improvements in a PUF. Second, we present a large-scale PUF characterization method to validate the efficiency of a PUF as a secure primitive. A compact and portable method measured a sizable set of around 200 chips. We also performed experiments to test a PUF against variations in operating conditions (temperature, supply voltage) and circuit aging. Third, we propose a method that can evaluate and compare the performance of different PUFs irrespective of their underlying working principles. This method can help a designer to select a PUF that is the most suitable one for a particular application. Finally, a novel PUF that exploits the variability in the pipeline of a microprocessor is presented. This PUF has a very low area cost while it can be easily integrated using software programs in an application having a microprocessor. / Ph. D.

As we scale down each process generation the degree of control we have on device parameters decreases. We are left to contend with a great deal of variability in process and environmental parameters. Process variation impacts dopant concentration, channel length, oxide thickness and other device parameters. Temperature variation too affects several parameters, amongst them are the threshold voltage and carrier mobility. All of these variations can either be margined for during design or compensated for dynamically. In this paper the technique of adaptive body bias is successfully applied to compensate for the variation in design so that the circuit operates at no more than 10 percent of the optimal pvt (process voltage temperature) point while minimizing leakage. / text

VLSI circuits in nanometer VLSI technology experience significant variations - intrinsic process variations and variations brought about by transistor degradation or aging. These are generally embodied by yield loss or performance degradation over operation time. Although the degradation can be compensated by the worst-case scenario based over-design approach, it induces remarkable power overhead which is undesirable in tightly power-constrained designs. Dynamic voltage scaling (DVS) is a more powerefficient approach. However, its coarse granularity implies difficulty in handling finegrained variations. These factors have contributed to the growing interest in poweraware robust circuit design. In this thesis, we propose a Built-In Proactive Tuning (BIPT) system, a lowpower typical case design methodology based on dynamic prediction and prevention of possible circuit timing errors. BIPT makes use of the canary circuit to predict the variation induced performance degradation. The approach presented allows each circuit block to autonomously tune its performance according to its own degree of variation. The tuning is conducted offline, either at power on or periodically. A test pattern generator is included to reduce the uncertainty of the aging prediction due to different input vectors. The BIPT system is validated through SPICE simulations on benchmark circuits with consideration of process variations and NBTI, a static stress based PMOS aging effect. The experimental results indicate that to achieve the same variation resilience, proposed BIPT system leads to 33% power savings in case of process variations as compared to the over-design approach. In the case of aging resilience, the approach proposed in this thesis leads to 40% less power than the approach of over-design while 30% less power as compared to DVS with NBTI effect modeling.