The continued scaling of feature size in silicon (Si)-based complimentary metal-oxide-semiconductor (CMOS) technology has led to a rapid increase in compute power. Resulting from increases in device densities and advances in materials and transistor design, integrated circuit (IC) performance has continued to improve while operational power (VDD) has been substantially reduced. However, as feature sizes approach the atomic length scale, fundamental limitations in switching characteristics (such as subthreshold slope, SS, and OFF-state power dissipation) pose key technical challenges moving forward. Novel material innovations and device architectures, such as group IV and III-V materials and tunnel field-effect transistors (TFETs), have been proposed as solutions for the beyond Si era. TFETs benefit from steep switching characteristics due to the band-to-band tunneling injection of carriers from source to channel. Moreover, the narrow bandgaps of III-V and germanium (Ge) make them attractive material choices for TFETs in order to improve ON-state current and reduce SS. Further, Ge grown on InₓGa₁₋ₓAs experiences epitaxy-induced strain (ε), further reducing the Ge bandgap and improving carrier mobility. Due to these reasons, the ε-Ge/InₓGa₁₋ₓAs system is a promising candidate for future TFET architectures. In addition, the ability to tune the bandgap of Ge via strain engineering makes ε-Ge/InₓGa₁₋ₓAs heterostructures attractive for nanoscale group IV-based photonics, thereby benefitting the monolithic integration of electronics and photonics on Si. This research systematically investigates the material, optical, and heterointerface properties of ε-Ge/InₓGa₁₋ₓAs heterostructures on GaAs and Si substrates. The effect of strain on the heterointerface band alignment is comprehensively studied, demonstrating the ability to modulate the effective tunneling barrier height (Ebeff) and thus the threshold voltage (VT), ON-state current, and SS in future ε-Ge/InₓGa₁₋ₓAs TFETs. Further, band structure engineering via strain modulation is shown to be an effective technique for tuning the emission properties of Ge. Moreover, the ability to heterogeneously integrate these structures on Si is demonstrated for the first time, indicating their viability for the development of next-generation high performance, low-power logic and photonic integrated circuits on Si. / Master of Science

The Tunnel Field Effect Transistor (TFET) with sub-60mV/decade Sub-threshold slope and extremely high ION/IOFF ratio has attracted enough attention for low standby power (LSTP) applications where the battery life is very important. So far research in this area has been limited to numerical simulation and experimental analysis. It is however extremely necessary to develop compact models for TFET in order to use them in nano-scale integrated circuit design and simulation. In this work, for the first time, we develop analytical Sub-threshold slope model for n-channel double gate TFET (nDGTFET). Unlike conventional FETs, current in TFET is mainly controlled by the band-to-band tunneling mechanism at source/channel interface. As the total drain current is proportional to band-to-band generation rate, the main challenge in the present work is to find an explicit relationship between average electric field over the tunneling path and the applied gate voltage under nonlocal tunneling condition. Two dimensional Poisson’s equation (with Laplace approximation)is first solved in a rectangular coordinate system in order to obtain analytical expression for electron energy distribution over the channel region.Kane’s Model[J. Phy. Chem.Solids 12(181)1959]for band-to-band tunneling along with some analytical approximation techniques are then used to derive the expression for the Sub-threshold slope under nonlocal tunneling conditions. This Sub-threshold slope model is verified against professional numerical device simulator (MEDICI) for different device geometries. Being an asymmetric device, TFET fabrication suffers from source misalignment with gate. As the doping in source and drain-gate are different, conventional-FET-like self-aligned gate stack formation is not possible for TFET. Such misalignment, at source side, seriously degrades the performance of TFETs. To overcome this problem, in this work we explore the possibility of using “gate replacement” technique for TFET fabrication. We first develop process flow for single gate bulk nTFET, and then we extend it to n-channel double gate TFET (nDGTFET) using modified FinFET process. Good alignments between source and gate are observed with TCAD-simulations in both the cases.

Reducing supply voltage is a promising way to address the power dissipation in nano-electronic circuits. However, the fundamental lower limit of subthreshold slope (SS) within metal-oxide-semiconductor field-effect transistors (MOSFETs) is a major obstacle to further scaling the operation voltage without degrading ON/OFF-ratio in today's integrated circuits. Tunnel field-effect transistors (TFETs) benefit from steep switching characteristics due to the quantum-mechanical tunneling injection of carriers from source to channel, rather than by conventional thermionic emission in MOSFETs. TFETs based on group III-V compound semiconductor and Ge heterostructures further improve the ON-state current and reduce SS due to the low bandgap energies and smaller carrier tunneling mass. The mixed arsenide/antimonide (As/Sb) InxGa1-xAs/GaAsySb1-y and Ge/InxGa1-xAs heterostructures allow a wide range of bandgap energies and various band alignments depending on the alloy compositions in the source and channel materials. Band alignments at source/channel heterointerface can be well modulated by carefully controlling the compositions of the InxGa1-xAs or GaAsySb1-y. In particular, this research systematically investigate the development and optimization of low-power TFETs using mixed As/Sb and Ge/InxGa1-xAs based heterostructures including: basic working principles, design considerations, material growth, interface engineering, material characterization, band alignment determination, device fabrication, device performance investigation, and high-temperature reliability. A comprehensive study of TFETs using mixed As/Sb and Ge/InxGa1-xAs based heterostructures shows superior structural properties and distinguished device performances, both of which indicate the mixed As/Sb and Ge/InxGa1-xAs based TFET as a promising option for high performance, low standby power and energy efficient logic circuit application. / Ph. D.