Many researchers and engineers designing laser drivers for data rates at or above 10 gigabits per second (Gbps) implemented their designs using integrated circuit technologies that provide high bandwidth and good quality passive components such as GaAs, silicon bipolar, and InP. However, in low-cost and high volume short-haul applications at data rates of around 10 Gbps (such as LAN, MAN, and board-to-board interconnection), there has been an increasing interest in commercial CMOS technology for implementing the laser driver. This is because CMOS technology has unique advantages such as low power and low cost of fabrication that are the result of high yield and a high degree of integration. Therefore, the objective of this research in this dissertation is to investigate the possibility of implementing a high-speed CMOS laser driver for these cost sensitive applications. The high-speed CMOS laser drivers designed in this research are of two types. The first type is a low power laser driver for driving a vertical cavity surface emitting laser (VCSEL). The other driver type is a high current laser driver for driving edge-emitting lasers such as double-heterojunction (DH), multiquantum well (MQW), or Febry-Perrot (FP) lasers. The parasitic effects of the layout geometry are crucial in the design of the high-speed laser drivers. Thus, in this research, all simulations contain a complete set of parasitic elements extracted from the layout of the laser driver. To test laser drivers, chip-on-board (COB) technology is employed, and printed circuit boards (PCBs) to test the laser drivers are designed at the same time as the laser drivers themselves and manufactured specifically for these tests. This research makes two significant new contributions to the technology that are reported and described here. One is the first 10 Gbps performance of a differential CMOS laser driver with better than 10-14 bit-error-rate (BER). The second is the first demonstration of a heterogeneous integration method to integrate independently grown and customized thin film lasers onto CMOS laser driver circuits to form an optical transmitter.

In this dissertation, the development of an experimental prototype for on-board optical-to-electrical signal broadcasting at 10 Gb/s per channel over an interconnect distance of 10 cm was presented. The optical distribution network was implemented using a polymer-based 1-by-4 multimode interference (MMI) splitter with linearly tapered output facet. A 1-by-8 MMI splitter with input/output waveguides of 10 microns in width was first fabricated using standard photolithography and characterized at 40 Gb/s in NRZ format and PRBS = 2^7-1. The pulse response of MMI devices was further quantified from the time-dependent, pulse-modulated field propagation perspective incorporated with various dispersion mechanisms. The results predict their operating limitations and investigate why and how such devices become non-functional in the ultrashort-pulse limit that is far beyond the most present-day optical systems. The guided-mode attenuation associated with polymer waveguides fabricated on FR-4 printed-circuit boards was also investigated for the first time. The rigorous transmission-line network approach was applied and the FR-4 substrate was treated as a long-period substrate grating with rectangular corrugations. The peaks of attenuation were shown to occur near the Bragg conditions that were recognized as the leaky-wave stop bands. As the buffer layer thickness increases, the attenuation becomes negligibly small that is attributed to the weak grating-induced perturbation to the mode behavior. The prototype was then developed on the basis of both experimental verifications to the devices and theoretical investigations. An improved 1-by-4 MMI splitter at 1550 nm with linearly tapered output facet was heterogeneously integrated with four p-i-n photodetectors (PDs) on a silicon (Si) bench. The Si bench itself was then hybrid integrated onto an FR-4 printed-circuit board with four receiver channels composed of transimpedance amplifiers, limiting amplifiers, and surface-mounted components. The innovative integration approach demonstrated the simultaneous alignment between multiple waveguides and multiple PDs during the MMI fabrication process that is a complete radical departure from the conventional assembly method inherent from the telecommunication industry. The entire system was fully functional at 10 Gb/s per channel.

<p>The integration of planar on-chip light sources is a bottleneck in the implementation of portable planar chip-scale photonic integrated sensing systems, integrated optical interconnects, and optical signal processing systems on platforms such as Silicon (Si) and Si-CMOS integrated circuits. A III/V on-chip laser source integrated onto Si needs to use standard semiconductor fabrication techniques, operate at low power, and enable efficient coupling to other devices on the Si platform.</p><p>In this thesis, thin film strain compensated InGaAs/GaAs single quantum well (SQW) separate confinement heterostructure (SCH) edge emitting lasers (EELs) have been implemented with patterning on both sides of the thin film laser under either growth or host substrate support, with the devices metal/metal bonded to Si and SiO₂/Si substrates. Gain and index guided lasers in various configurations fabricated using standard semiconductor manufacturing processes were simulated, fabricated, and experimentally characterized. Low threshold current densities in the range of 250 A/cm<super>2</super> were achieved. These are the lowest threshold current densities achieved for thin film single quantum well (SQW) lasers integrated on Si reported to date, and also the lowest reported, for thin film lasers operating in the 980 nm wavelength window.</p><p>These thin film EELs were also integrated with photolithographically patterned polymer (SU-8) waveguides on the same SiO₂/Si substrate. Coupling of the laser and waveguide was compared for the cases where an air gap existed between the thin film laser and the waveguide, and in which one facet of the thin film laser was embedded in the waveguide. The laser to waveguide coupling was improved by embedding the laser facet into the waveguide, and eliminating the air gap between the laser and the waveguide. Although the Fresnel reflectivity of the embedded facet was reduced by embedding the facet in the polymer waveguide, leading to a 27.2% increase in threshold current density for 800 &mum long lasers, the slope efficiency of the L-I curves was higher due to preferential power output from the front (now lower reflectivity) facet. In spite of this reduced mirror reflectivity, threshold current densities of 260 A/cm<super>2</super> were achieved for 1000 &mum long lasers. This passively aligned structure eliminates the need for precise placement and tight tolerances typically found in end-fire coupling configurations on separate substrates.</p> / Dissertation

La photonique sur silicium connaît depuis plusieurs années un fort développement avec la démonstration d’importants résultats concernant les interconnexions optiques. En effet, l’explosion du trafic de données au sein des centres de données a nécessité de trouver une solution annexe aux interconnexions métalliques afin de supporter de très hauts débits de transmission, tout en assurant une faible consommation énergétique et un coût raisonnable. Les applications de la photonique se situent d’une part dans le domaine des communications à longue distance entre équipements dont les standards actuels visent un débit de 400 Gb/s, et d’autre part dans le domaine des calculateurs à haute performance afin de réaliser les interconnexions courte distance entre un processeur et une banque de mémoires.STMicroelectronics s’est lancé depuis 2012 dans le développement d’une plateforme photonique sur silicium sur wafers de 300mm. Les principaux objectifs sont : la conception des composants optiques passifs et actifs pour réaliser un transceiver élémentaire à un débit de 20 Gb/s, l’intégration accrue des dispositifs électro-optiques afin de constituer un interposeur photonique, la capacité à gérer plusieurs longueurs d’onde.Dans ce contexte, le sujet de cette thèse porte sur la mise au point d’un circuit de qualification proposant l’intégration d’un transmetteur électro-optique à l’échelle de la puce.Cette solution tire bénéfice de l’architecture de l’assemblage en trois dimensions des éléments constitutifs au sein de l’interposeur et permet de traiter l’hétérogénéité des composants électriques et optiques.Dans ces travaux, nous proposons dans un premier temps d’étudier le modulateur optique. Celui-ci repose sur l’utilisation d’un anneau résonant dont la bande passante est optimisée afin de permettre des débits jusqu’à 50 Gb/s. Dans un second temps, nous décrivons la conception du driver électrique en technologie CMOS 55nm et expliquons le compromis mis en jeu entre la vitesse et la puissance consommée par le transmetteur. Les deux dispositifs sont fabriqués sur des plateformes distinctes, puis caractérisés et analysés par rapport à leur modèle respectif. Puis, nous réalisons une première intégration du transmetteur complet via un assemblage wire-bonding, ce qui nous permet de valider son fonctionnement et d’identifier les difficultés d’une telle co-intégration. Enfin, la dernière partie de la thèse est consacrée à la préparation d’un démonstrateur intégrant, dans un assemblage 3D à base de micro-piliers en cuivre, un lien électro-optique capable de transmettre 16 canaux à 20 Gb/s. Le multiplexage en longueurs d’onde déployé dans ce lien devrait permettre d’atteindre un débit total de 320 Gb/s. De plus, l’étude énergétique du système permet de s’assurer que l’interconnexion finale respectera les contraintes de consommation de puissance. / Stimulated by a series of important breakthrough, silicon photonics has been experiencing a significant development for several years. Indeed, due to exponential growth of data traffic inside datacenters, an alternative solution to metallic interconnects has been proposed to address very high transmission rates while ensuring a low energy consumption and a reasonable cost. Promising applications are in the field of both long- and short-distance optical communications. Long-range interconnects between datacenter equipment currently target an aggregate throughput of 400 Gb/s while short-reach interconnects are involved in high performance computers between a processor and a memory bank.STMicroelectronics has been developing a silicon photonic platform on 300 mm wafers since 2012. The main objectives are: the design of passive and active optical components to achieve an elementary 20 Gb/s transceiver, the increased integration of electro-optic devices to form a photonic interposer, the ability to manage several wavelengths.In this context, this PhD report deals with a testchip development at wafer level, proposing the integration of anelectro-optic transmitter. This solution benefits from the three dimensions assembly architecture of the dies within the photonic interposer and can handle the heterogeneity of electrical and optical components.This work first proposes to study the optical modulator which is based on a ring resonator. The ring bandwidth is optimized to operate up to 50 Gb/s. Secondly, the 55nm CMOS electrical driver design is described and the trade-off between transmitter speed and power consumption is highlighted. Both devices are fabricated on distinct technological platforms, then characterized and analyzed with respect to their respective models. A first integration of the complete transmitter is assembled through wire-bonding method, which enables to validate the transmitter operation. Finally, the last part of the report is devoted to the preparation of a 3D demonstrator based on micro-copper pillars assembly. The demonstrator integrates a wavelength division multiplexed link with 16 channels, which is expected to achieve a total throughput of 320 Gb/s. In addition, the system study enables to ensure that the final interconnect will respect power consumption constraints.

Este trabalho, desenvolvido junto ao Grupo de Novos Materiais e Dispositivos (GNMD) pertencente ao Laboratório de Microeletrônica (LME) da Universidade de São Paulo, apresenta a modelagem de um defasador passivo miniaturizado com baixas perdas para aplicações em ondas milimétricas (mmW-milimeter waves). Este defasador é baseado em um conceito inovador utilizando sistemas micro-eletromecânicos (MEMS) distribuídos e linhas de transmissão coplanares de ondas lentas. Este conceito é proposto no projeto Jovem Pesquisador FAPESP (Processo no. 2011/18167-3), ao qual este projeto está vinculado. A defasagem neste tipo de dispositivo é conseguida pela liberação das fitas da camada de blindagem de uma linha de transmissão tipo S-CPW (Shielded-Coplanar Waveguide). As fitas liberadas podem ser movimentadas eletrostaticamente, o que praticamente não consome energia. Este projeto pretende projetar um defasador para fabricação com a tecnologia do Laboratório de Microeletrônica da Escola Politécnica da Universidade de São Paulo. Adicionalmente, este trabalho apresenta resultados experimentais de um processo de fabricação IN-HOUSE baseado na metodologia de integração por flip-chip. A tecnologia de integração implementada é baseada na soldagem de um chip sobre um substrato, no qual são construídos uma nova geração de pilares de cobre finos, cujo espaçamento entre pilares é menor que 100 ?m. Essa redução nas dimensões pode ser usada com a nova geração de dispositivos de comunicações na faixa das mmW. Em termos de fabricação, foram obtidos pilares de cobre altamente miniaturizados com uma altura significativa e uniforme que permite a integração com o chip. Além do mais, os resultados obtidos representam avanços significativos no processo de fabricação que será usado como tecnologia de integração híbrida em um interposer baseado em substrato de alumina nanoporosa (MnM-Metallic Nanowire Membrane). Esse interposer desempenha um papel indispensável no GNMD, já que atualmente estão sendo estudadas suas propriedades elétricas e já foram construídos dispositivos sobre o substrato com resultados promissores. / This work, performed at the New Materials and Devices Group (GNMD) of the Microelectronics Laboratory of the Polytechnic School of the University of São Paulo, presents the modeling of a miniaturized passive phase shifter with low losses for applications in millimeter waves. It is based on an innovated concept, which uses distributed MEMS phase shifters and slow-wave coplanar wave guides. Such concept is proposed under the FAPESP Youth Researcher project (Process number 2011/18167-3). The phase shifter on this kind of device is achieved by releasing the shielding layer of the Shielded-Coplanar Waveguide. The released ribbons are electrostatically displaced, which does not consume energy. The aim of this project is to design a phase shifter for fabrication with the technology available at the Microelectronics Laboratory. Additionally, this work presents experimental results of a flip-chip fabrication process. This technology is based on next generation of fine pitch copper pillar bumping, with pillar pitch of less than 100 ?m that support next generation of communication devices at the millimeter wave frequency range. From the fabrication point-of-view, highly miniaturized copper pillars with appropriate thicknesses were obtained. Furthermore, the results obtained represent a significant advance in the fabrication process that will be used as a hybrid integration technology on an interposer based on a nanoporous alumina substrate (MnM-Metallic Nanowire Membrane).

Este trabalho, desenvolvido junto ao Grupo de Novos Materiais e Dispositivos (GNMD) pertencente ao Laboratório de Microeletrônica (LME) da Universidade de São Paulo, apresenta a modelagem de um defasador passivo miniaturizado com baixas perdas para aplicações em ondas milimétricas (mmW-milimeter waves). Este defasador é baseado em um conceito inovador utilizando sistemas micro-eletromecânicos (MEMS) distribuídos e linhas de transmissão coplanares de ondas lentas. Este conceito é proposto no projeto Jovem Pesquisador FAPESP (Processo no. 2011/18167-3), ao qual este projeto está vinculado. A defasagem neste tipo de dispositivo é conseguida pela liberação das fitas da camada de blindagem de uma linha de transmissão tipo S-CPW (Shielded-Coplanar Waveguide). As fitas liberadas podem ser movimentadas eletrostaticamente, o que praticamente não consome energia. Este projeto pretende projetar um defasador para fabricação com a tecnologia do Laboratório de Microeletrônica da Escola Politécnica da Universidade de São Paulo. Adicionalmente, este trabalho apresenta resultados experimentais de um processo de fabricação IN-HOUSE baseado na metodologia de integração por flip-chip. A tecnologia de integração implementada é baseada na soldagem de um chip sobre um substrato, no qual são construídos uma nova geração de pilares de cobre finos, cujo espaçamento entre pilares é menor que 100 ?m. Essa redução nas dimensões pode ser usada com a nova geração de dispositivos de comunicações na faixa das mmW. Em termos de fabricação, foram obtidos pilares de cobre altamente miniaturizados com uma altura significativa e uniforme que permite a integração com o chip. Além do mais, os resultados obtidos representam avanços significativos no processo de fabricação que será usado como tecnologia de integração híbrida em um interposer baseado em substrato de alumina nanoporosa (MnM-Metallic Nanowire Membrane). Esse interposer desempenha um papel indispensável no GNMD, já que atualmente estão sendo estudadas suas propriedades elétricas e já foram construídos dispositivos sobre o substrato com resultados promissores. / This work, performed at the New Materials and Devices Group (GNMD) of the Microelectronics Laboratory of the Polytechnic School of the University of São Paulo, presents the modeling of a miniaturized passive phase shifter with low losses for applications in millimeter waves. It is based on an innovated concept, which uses distributed MEMS phase shifters and slow-wave coplanar wave guides. Such concept is proposed under the FAPESP Youth Researcher project (Process number 2011/18167-3). The phase shifter on this kind of device is achieved by releasing the shielding layer of the Shielded-Coplanar Waveguide. The released ribbons are electrostatically displaced, which does not consume energy. The aim of this project is to design a phase shifter for fabrication with the technology available at the Microelectronics Laboratory. Additionally, this work presents experimental results of a flip-chip fabrication process. This technology is based on next generation of fine pitch copper pillar bumping, with pillar pitch of less than 100 ?m that support next generation of communication devices at the millimeter wave frequency range. From the fabrication point-of-view, highly miniaturized copper pillars with appropriate thicknesses were obtained. Furthermore, the results obtained represent a significant advance in the fabrication process that will be used as a hybrid integration technology on an interposer based on a nanoporous alumina substrate (MnM-Metallic Nanowire Membrane).

Les convertisseurs de puissance en DC/DC sont largement utilisés pour les applications domestiques et industrielles pour des puissances de quelques Watts à quelques MégaWatts. Généralement, pour chaque application un convertisseur adapté est conçu afin de répondre au cahier des charges. A chaque nouvelle application correspond donc un nouveau convertisseur, ce qui conduit à concevoir systématiquement de nouvelles structures de conversion et qui s'avère coûteux en temps et en argent. Eventuellement, cela peut conduire à des développements technologiques spécifiques qui, eux aussi ont des conséquences sur le coût de développement des solutions d'électronique de puissance.Afin de contourner ces difficultés, mes travaux de thèse portent sur la démarche Réseaux de Micro Convertisseurs (RµC) qui propose une nouvelle approche permettant de répondre de manière totalement flexible à n’importe quel cahier des charges. Cette approche vise à créer un composant unique, appelé cellule élémentaire (CE), permettant de répondre à tout type de cahiers des charges par la mise en série et/ou en parallèle de plusieurs de ces cellules élémentaires. Elle permet ainsi de régler les calibres en tension et/ou en courant du convertisseur à réaliser. Mes travaux de thèse se divisent en deux grandes parties. La première partie consiste en la conception et l’intégration de la cellule élémentaire utilisée dans le RµC. La deuxième, aborde les stratégies de configuration utilisées dans les RµC ainsi que les modes d’association des cellules élémentaires pouvant répondre à n’importe quel cahier des charges. / DC/DC power converters are widely used for domestic and industrial applications with powers from a few watts to several MegaWatts. Generally, for each application, an appropriate converter is designed to meet the specifications. So, with a new application corresponds a new converter leading to systematic review and re-design of a new structure of conversion which is costly in time and money. Eventually, it can lead to specific technological developments which also have an impact on the cost of developing solutions for power electronics. To circumvent these difficulties, my thesis focuses on the process of Micro Converters Networks (MiCoNet) which proposes a new approach to respond fully flexibely to any specifications. The aim of this approach is to create a unit component, called elementary cell, able to respond to any kind of specifications by connecting in series and/or parallel several of these elementary cells. It permits to adjust the voltage and/or current of the converter to achieve. Therefore, my thesis is divided into two main parts. The first part consists in the design and the integration of the elementary cell used in the MiCoNet. The second discusses the configuration strategies used in the MiCoNet and association modes of elementary cells which can respond to any specification.

In this thesis, we present a graphical computer-aided design (CAD) environment for the design, analysis and layout of printed electronic batteries in the first phase and the parasitic extraction of the connecting wires in the second phase. The primary motivation of our work is that this prototyping software tool so far does not exist. Our tool has been integrated within the existing CAD tool which allows quick prototyping and simplifies the interface between the system designer and the device manufacturer. This tools supports the schematic and layout entry, rule checking and netlist generation. The first phase of the device synthesis modelling is based on Enfucell printed batteries, by which using the CAD tool, the shape of the battery is optimized and designed to fit the product and is able to simulate the performance during the optimization, whereas the second phase is the parasitic extraction using an extracting tool named fasthenry, which is integrated to our CAD tool to extract unwanted resistance and inductance within the shared wires between the battery and other devices. We believe that the availability of this tool is useful to the CAD community for novel ideas in the circuit design for flexible hybrid electronics. / +46764354255, +46722694942

L’émergence des satellites très haut débit pour la couverture des zones rurales s’accompagne de nombreuses contraintes technologiques. Dans le cadre du plan France très haut débit, le projet THD-sat proposé par le CNES se base sur l’utilisation des bandes Q et V pour assurer les liaisons avec les stations au sol et libérer de la ressource sur la bande Ka communément utilisée par les satellites ancienne génération. Avec la montée en fréquence, les besoins en termes de filtrage deviennent très stricts nécessitant des considérations particulières. Le premier chapitre reprend le contexte de l’étude et expose les différents éléments permettant de justifier le choix de la technologie SIW qui profite à la fois des bons facteurs de qualité des modes volumiques se propageant dans le substrat et de l’aisance du procédé technologique et de l’intégration des structures planaires. Les performances des cavités SIW restent néanmoins intimement liées à l’épaisseur de substrat qui doit être augmentée pour atteindre de meilleurs facteurs de qualité. L’augmentation de l’épaisseur de substrat s’accompagne de deux principales limitations : le rallongement des fils de « bonding » utilisés pour le câblage du filtre à son environnement MIC d’épaisseur 254 μm et l’élargissement de la ligne d’accès 50 Ω induisant des problèmes de discontinuités et d’excitations de modes parasites. L’approche suivie consiste à considérer des formes 3D permettant l’adaptation de mode et d’épaisseur entre une ligne microruban sur substrat de 254 μm d’épaisseur et le SIW d’épaisseur plus importante. Une nouvelle transition 3D est dès lors imaginée. Le chapitre II reprend les différents procédés technologiques utilisés pour la mise en forme et la métallisation des substrats 3D. Les substrats considérés sont l’alumine et la silice fondue mis en forme par ablation laser et le thermoplastique COP mis en forme par moulage. La principale limitation de l’ablation laser concerne les épaisseurs de substrat accessibles. Nous nous limitons à 635 μm dans le cas de l’alumine et à 500 μm dans le cas de la silice fondue. Le moulage polymère permet de s’affranchir de cette limitation et de viser des substrats plus épais (2 mm pour la solution COP).Le chapitre III reprend les étapes de conception des différentes solutions de filtrage avec la nouvelle transition 3D. Des résultats de mesures de différents prototypes réalisés sont par ailleurs présentés. Ces résultats sont globalement encourageants mais nécessitent d’être davantage développés pour être mieux exploitables. / The emergence of satellite high-speed internet for the coverage of rural zones is accompanied by numerous technological constraints. The current trend is to use higher frequency bands to release the satellite capacity for users. The increasing frequency requires new considerations especially for filtering needs which become notably strict in terms of performance and integration in small integrated circuits. This work introduces filtering solutions based on high quality factor Substrate Integrated Waveguides (SIW) using a novel 3D transition for a better integration in widely planar Hybrid ICs.The first chapter introduces the study’s context and the different elements justifying the use of the SIW technology.In fact, these structures profit from both the good quality factors of TE-modes propagating in the substrate and the easy fabrication process and integration of planar circuits. However, to increase the SIW quality factor, the substrate’s height should be increased which induces interconnection limitations such as long bond wires with high parasitic effects and large microstrip access lines with discontinuity problems and the propagation of parasitic modes. The adopted approach consists in imagining 3D shapes providing both mode and thickness matching between a microstrip line etched on a thin substrate and a high substrate SIW.The second chapter introduces the different manufacturing processes used for the substrate’s shaping and metallization. Three substrates are considered: Alumina, fused Silica and Cyclo Olefin Polymer COC. Alumina is widely used in space applications and has a well-mastered process. For equivalent dielectric losses, fused silica has a lower permittivity for bigger structures with less manufacturing tolerance sensitivity. Both Alumina and fused silica substrates are shaped using a laser ablation. The reachable substrate’s height using this machining method is relatively low. The polymer solution (COP) is elaborated using a molding process allowing higher substrates heights.The last chapter outlines the design steps of the different solutions and the measurement results of the first prototypes. These results are on the whole encouraging but require further development.

In dieser Arbeit wird das Stickstoff-Fehlstellenzentrum (NV Zentrum) in Diamant als ein solcher Einzelphotonenemitter untersucht. Durch Benutzung eines hybriden Ansatzes werden hier NV Zentren in Diamantnanopartikeln in photonische Strukturen integriert. Zuerst wird eine aufnehmen-und-ablegen-Nanomanipulationstechnik mittels eines Rasterkraftmikroskops verwendet um einzelne NV Zentren an eine photonische Kristallkavität und eine optische Faser zu koppeln. Durch Kopplung an die photonische Kristallkavität wird die Emission der Nullphononenlinie des NV Zentrums um den Faktor 12.1 erhöht und durch Kopplung an die optische Faser entsteht eine direkt gekoppelte Einzelphotonenquelle hoher effektiver numerischer Apertur. Durch Kopplung an plamonische Wellenleiter können einzelne Oberflächenplasmon-Polaritonen nachgewiesen werden. Zweitens wird ein anderer Ansatz, die Entwicklung eines hybriden Materials, verfolgt. Hier sind die Nanodiamanten, anstatt sie auf die Strukturen von Interesse zu legen, von Anfang in dem Material enthalten, aus dem die Strukturen hergestellt werden. Mittels direktem Zweiphotonen-Laserschreiben ist es dann möglich, Kombinationen aus chipintegrierten Wellenleitern, Resonatoren und Einzelphotonenemittern zu zeigen. Um mehr über die Dynamik von NV Zentren in Nanodiamant zu erfahren und Wege zu ihrer Verbesserung zu finden, wird die Dynamik der Nullphononenlinie des NV Zentrums mittels eines Photonenkorrelationsinterferometers untersucht. Zusätzlich zu Techniken zur Herstellung photonischer und plasmonischer Strukturen werden auch Methoden zu ihrer Charakterisierung benötigt. Hier für kann es ausgenutzt werden, dass das NV Zentrum weiter nicht nur ein Einzelphotonenemitters ist, sondern es ebenso als Sensor verwendet werden kann. Das NV Zentrum wird hier verwendet, um die lokale optische Zustandsdichte in einem Rastersondenverfahren zu messen, was die Technik der dreidimensionalen Quantenemitter Fluoreszenzlebensdauermikroskopie einführt. / In this thesis, one of such single photon emitters, the nitrogen vacancy centre (NV centre) in diamond, will be examined. By using different hybrid approaches, NV centres in diamond nanoparticles are integrated into photonic structures. Firstly, using a pick-and-place nanomanipulation technique with an atomic force microscope, a single NV centre is coupled to a photonic crystal cavity and an optical fibre. Coupling to the photonic crystal cavity results in an enhancement of the NV centre''s zero phonon line by a factor of 12.1 and coupling to the fibre yields a directly coupled single photon source with an effective numerical aperture of 0.82. By coupling to plasmonic waveguides, the signature of single surface plasmon polaritons is found. Secondly, instead of placing the nanodiamonds on the structures of interest, a hybrid material where the emitters are incorporated is used. With two-photon direct laser writing, on-chip integration and combination of waveguides, resonators, and single photon emitters is demonstrated. In order to learn more on the dynamics of NV centre in nanodiamonds and find ways for improvements, the dynamics of the ultra-fast spectral diffusion of the NV centre''s zero phonon line are investigated using a photon correlation interferometer. In addition to techniques for the fabrication of photonic and plasmonic structures, also methods for their characterisation are needed.For this, it can be exploited that the NV centre also is not only a single photon emitter, but can also be employed as a sensor. Here, the NV centre is used to measure the local density of optical states in a scanning probe experiment, establishing the technique of three-dimensional quantum emitter fluorescence lifetime imaging.