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Multi- and many-core processors are becoming increasingly popular in embedded systems. Many of these processors now feature hardware virtualization capabilities, such as the ARM Cortex A15, and x86 processors with Intel VT-x or AMD-V support. Hardware virtualization offers opportunities to partition physical resources, including processor cores, memory and I/O devices amongst guest virtual machines. Mixed criticality systems and services can then co-exist on the same platform in separate virtual machines. However, traditional virtual machine systems are too expensive because of the costs of trapping into hypervisors to multiplex and manage machine physical resources on behalf of separate guests. For example, hypervisors are needed to schedule separate VMs on physical processor cores. Additionally, traditional hypervisors have memory footprints that are often too large for many embedded computing systems. This dissertation presents the design of the Quest-V separation kernel, which partitions services of different criticality levels across separate virtual machines, or sandboxes. Each sandbox encapsulates a subset of machine physical resources that it manages without requiring intervention of a hypervisor. In Quest-V, a hypervisor is not needed for normal operation, except to bootstrap the system and establish communication channels between sandboxes. This approach not only reduces the memory footprint of the most privileged protection domain, it removes it from the control path during normal system operation, thereby heightening security.

This thesis proposed a near-field electromagnetic interference measurement framework to obtain sensitivity and spatial resolution of the characteristic parameters of magnetic probe based on International Electrotechnical Commission proposed for integrated circuits electromagnetic radiation measurement standards IEC 61967-6 : magnetic probe method. Using cross-coupled planar microwave bandpass filter which is realized by glass fiber board (FR4) for near-field measurement and electromagnetic simulation in comparsion. Nowadays, integrated circuits has become an important source of energy of overall electromagnetic interference in electronic systems. Finally, do near-field scanning measurement for a 64-pin wire-bond quad flat nonlead (WB-QFN) package and the voltage-controlled oscillator chip in 0.18 £gm CMOS technology by using high scanning resolution of microprobe. Then observes the chip-level and package-level electromagnetic interference, and achieve chip-level of near-field electromagnetic interference measurement techniques.

In this thesis, multiuser receivers for code division multiple-access (CDMA) downlink are studied under frequency selective fading channel conditions. The receivers investigated in this thesis attempt to estimate desired symbol as a linear combination of chip-rate sampled received signal sequence. A common matrix-vector representation of signals, which is similar to the model given by Paulraj et. al. is constructed in order to analyze the receivers studied in this thesis. Two receivers already well known in the literature are introduced and derived by using the common signal model. One of the receivers uses traditional matched filter and the other uses symbol-level linear minimum mean square error (MMSE) estimation. The receiver that uses traditional matched filter, also known as the conventional RAKE receiver, benefits from time diversity by combining the signal energy from multiple paths. The conventional RAKE receiver is optimal when multiple-access interference (MAI) is absent. Linear MMSE based receivers are known to suppress MAI and to be more robust to noise enhancement. The optimal symbol-level linear MMSE based receiver requires inversion of large matrices whose size is determined by either number of active users or spreading factor. These two parameters can be quite large in many practical systems and hence the computational load of this receiver can be a problem. In this thesis, two alternative low-complexity receivers, which are chip-level linear MMSE equalizer proposed by Krauss et. al. and interference-suppressing RAKE receiver proposed by Paulraj et. al., are compared with the linear full-rank MMSE based receiver and with the conventional RAKE receiver in terms of bit-error-rate performance. Various simulations are performed to evaluate the performance of the receivers and the parameters affecting the receiver performance are investigated.

The development of micro and nano-electromechanical systems (MEMS and NEMS) with entirely new or improved functionalities is typically based on novel or improved designs, materials and fabrication methods. However, today’s micro- and nano-fabrication is restrained by manufacturing paradigms that have been established by the integrated circuit (IC) industry over the past few decades. The exclusive use of IC manufacturing technologies leads to limited material choices, limited design flexibility and consequently to sub-optimal MEMS and NEMS devices. The work presented in this thesis breaks new ground with a multitude of novel approaches for the integration of non-standard materials that enable the fabrication of 3D micro and nanoelectromechanical systems. The objective of this thesis is to highlight methods that make use of non-standard materials with superior characteristics or methods that use standard materials and fabrication techniques in a novel context. The overall goal is to propose suitable and cost-efficient fabrication and integration methods, which can easily be made available to the industry. The first part of the thesis deals with the integration of bulk wire materials. A novel approach for the integration of at least partly ferromagnetic bulk wire materials has been implemented for the fabrication of high aspect ratio through silicon vias. Standard wire bonding technology, a very mature back-end technology, has been adapted for yet another through silicon via fabrication method and applications including liquid and vacuum packaging as well as microactuators based on shape memory alloy wires. As this thesis reveals, wire bonding, as a versatile and highly efficient technology, can be utilized for applications far beyond traditional interconnections in electronics packaging. The second part presents two approaches for the 3D heterogeneous integration based on layer transfer. Highly efficient monocrystalline silicon/ germanium is integrated on wafer-level for the fabrication of uncooled thermal image sensors and monolayer-graphene is integrated on chip-level for the use in diaphragm-based pressure sensors. The last part introduces a novel additive fabrication method for layer-bylayer printing of 3D silicon micro- and nano-structures. This method combines existing technologies, including focused ion beam implantation and chemical vapor deposition of silicon, in order to establish a high-resolution fabrication process that is related to popular 3D printing techniques. / <p>QC 20121207</p>