A new DC-DC up converter with high efficiency and low output ripple is proposed. We replace previous charge pump converters by switched-capacitor converters to improve the power efficiency and add a voltage regulator at the output to reduce the ripple voltage. The converter reduces the magnitude of output voltage ripples to 36% of the previous converter, and improves the power efficiency from 58% to 73%. The proposed converter is designed to obtain 1.6 mA driving capability with a output voltage around 5.3 ~ 5.4 V. A VCO is also added as the load to test the converter circuit. The VCO is insensititive to power supply noises. The proposed converter circuit is simulated in a TSMC 0.35-um Mixed-mode (2P4M) CMOS process.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0725103-101956 |
| Date | 25 July 2003 |
| Creators | Yang, Shun-Pin |
| Contributors | Jinn-Shyan Wang, Jyi-Tsong Lin, Yao-Tsong Tsai, Shyh-Jye Jou, Chia-Hsiung Kao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725103-101956 |
| Rights | campus_withheld, Copyright information available at source archive |
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