Cheung, Cheuk Kit. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references. / Abstract also in Chinese. / Abstract --- p.1 / 摘要 --- p.2 / Acknowledgements --- p.3 / Table of Contents --- p.4 / List of Figures --- p.9 / Chapter 1. --- Introduction --- p.12 / Chapter 1.1. --- Research Motivation --- p.12 / Chapter 1.1.1. --- Global and Intermediate Interconnects --- p.12 / Chapter 1.1.2. --- Constraints of Repeater Insertion Techniques --- p.13 / Chapter 1.2. --- Research Objective --- p.13 / Chapter 1.3. --- Reference --- p.14 / Chapter 2. --- Voltage Mode and Current Mode Circuits --- p.16 / Chapter 2.1. --- Introduction --- p.16 / Chapter 2.2. --- Voltage Mode Circuit --- p.16 / Chapter 2.3. --- Current Mode Circuit --- p.18 / Chapter 2.4. --- Power Consumption --- p.19 / Chapter 2.5. --- Latency --- p.20 / Chapter 2.6. --- Summary --- p.20 / Chapter 3. --- Transmitter Design --- p.22 / Chapter 3.1. --- Introduction --- p.22 / Chapter 3.2. --- Multi-level Signaling --- p.22 / Chapter 3.3. --- Gated Current Mirror --- p.23 / Chapter 3.4. --- Power Consumption --- p.24 / Chapter 3.5. --- Summary --- p.24 / Chapter 3.6. --- Reference --- p.25 / Chapter 4. --- Receiver Design --- p.26 / Chapter 4.1. --- Introduction --- p.26 / Chapter 4.2. --- Conventional Latched-typed Sense Amplifier --- p.27 / Chapter 4.3. --- Sense Amplifier with Isolated Differential Pair --- p.29 / Chapter 4.4. --- "Power Consumption, Latency and Kick-back Noise Comparison between Different Designs" --- p.30 / Chapter 4.4.1. --- Comparison on Power Consumption --- p.30 / Chapter 4.4.2. --- Comparison on Latency --- p.31 / Chapter 4.4.3. --- Comparison on Kick-back Noise --- p.33 / Chapter 4.5. --- Summary --- p.34 / Chapter 4.6. --- Reference --- p.34 / Chapter 5. --- Inverter Chain --- p.36 / Chapter 5.1. --- Introduction --- p.36 / Chapter 5.2. --- Inverter Chain Based --- p.36 / Chapter 5.3. --- Summary --- p.38 / Chapter 5.4. --- References --- p.38 / Chapter 6. --- Layout Techniques --- p.39 / Chapter 6.1. --- Introduction --- p.39 / Chapter 6.2. --- Two-Dimensional Common Centroid Layout Technique --- p.39 / Chapter 6.3. --- Dummy Devices --- p.40 / Chapter 6.4. --- Summary --- p.42 / Chapter 6.5. --- References --- p.42 / Chapter 7. --- Simulation Results --- p.43 / Chapter 7.1. --- Introduction --- p.43 / Chapter 7.2. --- Simulation of Different Aspect Ratios of Differential Pair --- p.43 / Chapter 7.3. --- System Level Simulation with Different Sense-amplifiers --- p.46 / Chapter 7.4. --- System Level Simulation at Different Data Rate --- p.47 / Chapter 7.5. --- Summary --- p.49 / Chapter 8. --- Measurement Results --- p.50 / Chapter 8.1. --- Introduction --- p.50 / Chapter 8.2. --- Experimental Setup --- p.50 / Chapter 8.2.1. --- Testing Chips --- p.50 / Chapter 8.2.2. --- Equipments Setup --- p.52 / Chapter 8.3. --- Measurement Results --- p.53 / Chapter 8.4. --- Summary --- p.56 / Chapter 9. --- Conclusion --- p.57 / Chapter 9.1. --- Author´ةs Contributions --- p.57 / Chapter 9.2. --- Future Works --- p.58 / Chapter 10. --- Appendix --- p.59
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_326818 |
| Date | January 2009 |
| Contributors | Cheung, Cheuk Kit., Chinese University of Hong Kong Graduate School. Division of Electronic Engineering. |
| Source Sets | The Chinese University of Hong Kong |
| Language | English, Chinese |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, 63 leaves : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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