The effect of die attach voiding on the thermal resistance of a hybrid integrated circuit package has been investigated. Voids with precisely controlled geometry, morphology, distribution, and different volume percentages are fabricated in the backside of the silicon chips by modern micro-photolithographic techniques. A large thin film resistor over the entire chip surface area served as a uniform heat generating source. A TO-3 steel package with beryllia substrate is used for chip packaging. Correlation of thermal resistance to power dissipation in the range studied is presented and discussed. The dependence of thermal resistance on void characteristics and total void area are demonstrated through infrared mapping of chip surface temperature; and the correlations are qualitatively analyzed. A brief discussion on die bond void reduction is also given.
| Identifer | oai:union.ndltd.org:arizona.edu/oai:arizona.openrepository.com:10150/276568 |
| Date | January 1987 |
| Creators | Chang, Li-hsin, 1946- |
| Contributors | Johnson, Barry C. |
| Publisher | The University of Arizona. |
| Source Sets | University of Arizona |
| Language | en_US |
| Detected Language | English |
| Type | text, Thesis-Reproduction (electronic) |
| Rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. |
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