Universal AHPL, a hardware description language, is supported by a function level simulator. Driving the simulation is a data base, generated by STAGE1 of the Three-Stage Hardware Compiler, and the output of the COMSEC Processor, which provides the user with control over the simulation and the printed results. This paper describes the design and use of the function level simulator HPSIM4A, a refined extension of its predecessor, HPSIM4. HPSIM4A is a thoroughly tested and debugged version of HPSIM4 with additional features that utilize more of Universal AHPL's descriptive capabilities. In particular, the multiple clock, the specific driving clock and the User-Defined Functional Register capabilities can now be simulated. Additionally, provision has been made to simulate both positive and negative edge triggered flip-flops and User-Defined Combinational Logic Units with a minimal programming effort.
| Identifer | oai:union.ndltd.org:arizona.edu/oai:arizona.openrepository.com:10150/292038 |
| Date | January 1989 |
| Creators | Brown, Joseph Nagy, 1959- |
| Contributors | Hill, Fredrick J. |
| Publisher | The University of Arizona. |
| Source Sets | University of Arizona |
| Language | en_US |
| Detected Language | English |
| Type | text, Thesis-Reproduction (electronic) |
| Rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. |
Page generated in 0.0019 seconds