Universal AHPL, a hardware description language, is supported by a function level simulator. Driving the simulation is a data base, generated by STAGE1 of the Three-Stage Hardware Compiler, and the output of the COMSEC Processor, which provides the user with control over the simulation and the printed results. This paper describes the design and use of the function level simulator HPSIM4A, a refined extension of its predecessor, HPSIM4. HPSIM4A is a thoroughly tested and debugged version of HPSIM4 with additional features that utilize more of Universal AHPL's descriptive capabilities. In particular, the multiple clock, the specific driving clock and the User-Defined Functional Register capabilities can now be simulated. Additionally, provision has been made to simulate both positive and negative edge triggered flip-flops and User-Defined Combinational Logic Units with a minimal programming effort.

Several methods to solve a system of linear equations with real and complex coefficients exist. The most popular methods are Gauss-Jordan, L-U Decomposition, Gauss-Seidel, and Matrix Reduction. These methods are utilized to optimize run-time of the DLANET circuit analysis program. As concluded by this study, the Matrix Reduction method which is presently utilized in the DLANET program, results in run-times which are faster than the other solution methods studied in this paper for lower order systems. Similarly, the L-U Decomposition and Gauss-Jordan methods result in faster run-times than the other techniques for higher order systems. Finally, the Gauss-Seidel Iterative method, when incorporated into the DLANET program, has proven to be much slower than the other solution methods considered in this paper.

A method for simulating the transient responses of networks containing lossless transmission lines and lumped parameter elements of circuits, both linear and nonlinear, has been developed and investigated. The method combines the technique of network analysis and that of modal decomposition of transmission lines. A prototype computer simulation program, called UANTL, based on the developed algorithm has been implemented. Several example networks have been simulated using this program. The results have been compared with those generated by the well known circuit simulator program called SPICE. UANTL has shown several advantages over SPICE in simulating the transient responses of networks containing transmission lines. A description of the prototype version of UANTL and a summary of the results of numerical experiments are included.

In search of higher speed and integration, the integrated circuit (IC) technology is scaling down. The total on-chip interconnect length is increasing exponentially. In fact, interconnect takes up the most part of the total chip area. The parasitics associated with these interconnect have significant impact on the circuit performance. Some of the effects of parasitics include cross talk, voltage drop and high current density. These issues can result in cross-talk induced functional failure and failures due to IR drop and electro-migration. This has resulted in interconnect- driven design trend in state-of-the-art integrated circuits. Reliability analysis, that includes simulating the effects of parasitics for voltage drop, current density, has become one of the most important steps in the VLSI design flow. Most of the CAD/EDA tools available, map these analysis results two dimensionally. Al- though this helps the designer, providing a three dimensional view of these results is highly desirable when dealing with complex circuits. In pursuit of visualizing reliability analysis results three dimensionally, as a first step, this work presents a tool that can visualize IC interconnect three di- mensionally. Throughout the course of this research open source tools were used to achieve the objective. In this work the circuit layout is stored as an OpenAc- cess database. A C++ program reads the design information using OpenAccess API and converts it to the .OBJ file format. Art of Illusion, an open source 3D modeling and rendering tool, reads this .OBJ file and models the IC interconnect three-dimensionally. In addition, Eclipse, an open source java IDE is used as a development platform. The tool presented has the capability to zoom in, zoom out and pan in real time.

A new method for transient simulation of integrated circuits has been developed and investigated. The method utilizes expansion of circuit variables into Chebyshev series. A prototype computer simulation program based on this technique has been implemented and applied in the transient simulation of several MOS circuits. The results have been compared with those generated by SPICE. The method has been also combined with the waveform relaxation technique. Several algorithms were developed using the Gauss-Seidel and Gauss-Jacobi iterative procedures. The algorithms based on the Gauss-Seidel iterative procedure were implemented in the prototype software. They offer substantial CPU time savings in comparison with SPICE without compromising the accuracy of solutions. A description of the prototype computer simulation program and a summary of the results of simulation experiments are included.

Fast methods for the electromagnetic simulation of integrated circuit (IC) package modules through model order reduction are demonstrated. The 3D integration of multiple functional IC chip/package modules on a single platform gives rise to geometrically complex structures with strong electromagnetic phenomena. This motivates our work on a fast full-wave solution for the analysis of such modules, thus contributing to the reduction in design cycle time without loss of accuracy. Traditionally, fast design approaches consider only approximate electromagnetic effects, giving rise to lumped-circuit models, and therefore may fail to accurately capture the signal integrity, power integrity, and electromagnetic interference effects. As part of this research, a second order frequency domain full-wave susceptance element equivalent circuit (SEEC) model will be extracted from a given structural layout. The model so obtained is suitably reduced using model order reduction techniques. As part of this effort, algorithms are developed to produce stable and passive reduced models of the original system, enabling fast frequency sweep analysis. Two distinct projection-based second order model reduction approaches will be considered: 1) matching moments, and 2) matching Laguerre coefficients, of the original system's transfer function. Further, the selection of multiple frequency shifts in these schemes to produce a globally representative model is also studied. Use of a second level preconditioned Krylov subspace process allows for a memory-efficient way to address large size problems.

Thesis (Ph.D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008. / Committee Chair: Prof. Madhavan Swaminathan; Committee Member: Prof. Andrew Peterson; Committee Member: Prof. Sungkyu Lim

A new optimization technique for SPICE modeling parameters has been developed in this dissertation to increase the accuracy of the circuit simulation. The importance of having accurate circuit simulation models is to prevent the very costly redesign of an Integrated Circuit (IC). This radically new optimization technique utilizes the Taguchi method to improve the fit between measured and simulated I-V curves for GaAs MESFETs. The Taguchi method consists of developing a Signal-to-Noise Ratio (SNR) equation that will find the optimum combination of controllable signal levels in a design or process to make it robust or as insensitive to noise as possible. In this dissertation, the control factors are considered the circuit model curve fitting parameters and the noise is considered the variation in the simulated I-V curves from the measured I-V curves. This is the first known application of the Taguchi method to the optimization of IC curve fitting model parameters. In addition, this method is not technology or device dependent and can be applied to silicon devices as well. Improvements in the accuracy of the simulated I-V curve fit reaching 80% has been achieved between DC test extracted parameters and the Taguchi optimized parameters. Moreover, the computer CPU execution time of the optimization process is 96% less than a commercial optimizer utilizing the Levenberg-Marquardt algorithm (optimizing 31 FETs). This technique does a least square fit on the data comparing measured currents versus simulated currents for various combinations of SPICE parameters. The mean and standard deviation of this least squares fit is incorporated in determining the SNR, providing the best combination of parameters within the evaluated range. Furthermore, the optimum values of the parameters are found without additional simulation by fitting the response curves to a quadratic equation and finding the local maximum. This technique can easily be implemented with any simulator that utilizes simulation modeling parameters extracted from measured DC test data. In addition, two methods are evaluated to obtain the worst case modeling parameters. One method lobks at the correlation coefficients between modeling parameters and the second looks at the actual device parameters that define the +/- 3σ limits of the process. Lastly, an example is given that describes the applicability of the Taguchi methodology in the design of a differential amplifier, that accounts for the effect of offset voltage. / Ph. D.

This paper describes a graphical representation technique for models in VHDL. The graphical representation is an extension of the Process Model Graph described in [1]. The Process Model Graph has representations for concurrent processes and signals. The representation described here, referred to as the Modified Process Model Graph, adds several new constructs to handle more features of VHDL. These new constructs include: variables inside process blocks, a visual notation for sensitivity lists, and a clear visual indication of the interface to an object. A software tool, called VHDLCad* (c)* * , has been developed that uses produces VHDL source code interactively from the graphical representation. The tool allows the user to use pre-defined modules, or create new modules and place them in the library. With the benefit of a graphical representation, a menu-driven system and re-usable code, VHDLCad can improve the productivity of VHDL modelers. *VHDLCad is a trademark of David G. Burnette. **Copyright 1988 by David G. Burnette. All rights reserved / Master of Science

The objective of this research work is to develop an efficient methodology for chip-package cosimulation. In the traditional design flow, the integrated circuit (IC) is first designed followed by the package design. The disadvantage of the conventional sequential design flow is that if there are problems with signal and power integrity after the integration of the IC and the package, it is expensive and time consuming to go back and change the IC layout for a different input/output (IO) pad assignment. To overcome this limitation, a concurrent design flow, where both the IC and the package are designed together, has been recommended by researchers to obtain a fast design closure. The techniques from this research work will enable multiscale cosimulation of the chip and the package making the concurrent design flow paradigm possible. Traditional time-domain techniques, such as the finite-difference time-domain method, are limited by the Courant condition and are not suitable for chip-package cosimulation. The Courant condition gives an upper bound on the time step that can be used to obtain stable simulation results. The smaller the mesh dimension the smaller is the Courant time step. In the case of chip-package cosimulation the on-chip structures require a fine mesh, which can make the time step prohibitively small. An unconditionally stable scheme using Laguerre polynomials has been recommended for chip-package cosimulation. Prior limitations in this method have been overcome in this research work. The enhanced transient simulation scheme using Laguerre polynomials has been named SLeEC, which stands for simulation using Laguerre equivalent circuit. A full-wave EM simulator has been developed using the SLeEC methodology. A scheme for efficient use of full-wave solver for chip-package cosimulation has been proposed. Simulation of the entire chip-package structure using a full-wave solver could be a memory and time-intensive operation. A more efficient way is to separate the chip-package structure into the chip, the package signal-delivery network, and the package power-delivery network; use a full-wave solver to simulate each of these smaller subblocks and integrate them together in the following step, before a final simulation is done on the integrated network. Examples have been presented that illustrate the technique.