This thesis reports on a new low-cost wafer-level packaging technology for microelectromechanical systems (MEMS). The MEMS process is based on a revised version of High Aspect Ratio Polysilicon and Single Crystal Silicon (HARPSS) technology. The packaging technique is based on thermal decomposition of a sacrificial polymer through a polymer overcoat followed by metal coating to create resizable MEMS packages. The sacrificial polymer is created on top of the active component including beams, seismic mass, and electrodes by photodefining, dispensing, etching, or molding. The low loss polymer overcoat is patterned by photodefinition to provide access to the bond pads. The sacrificial polymer decomposes at temperatures around 200-280aC and the volatile products permeate through the overcoat polymer leaving an embedded air-cavity. For MEMS devices that do not need hermetic packaging, the encapsulated device can then be handled and packaged like an integrated circuit. For devices that are sensitive to humidity or need vacuum environment, hermiticity is obtained by deposition and patterning thin-film metals such as aluminum, chromium, copper, or gold. To demonstrate the potential of this technology, different types of capacitive MEMS devices have been designed, fabricated, packaged, and characterized. These includes beam resonators, RF tunable capacitors, accelerometers, and gyroscopes. The MEMS design includes mechanical, thermal, and electromagnetic analysis. The device performance, before and after packaging is compared and the correlation to the model is presented. The following is a summary of the main contributions of this work to the extensive research focused on MEMS and their packaging: 1)A new low-cost wafer-level packaging method for bulk or surface micromachined devices including resonators, RF passives and mechanical sensors is reported. This technique utilizes thermal decomposition of a sacrificial polymer through an overcoat polymer to create buried channels on top of the resonant/movable parts of the micromachined device. It provides small interconnections together with resizable package dimensions. We report MEMS package thicknesses in the range of 10 mm to 1 mm, and package size from 0.0001 mm to 1 mm. 2)A revised version of the HARPSS technology is presented to implement high aspect ratio silicon capacitors, resonators and inertial sensors in the smallest area.

Thesis (Ph.D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008. / Committee Chair: Prof. Madhavan Swaminathan; Committee Member: Prof. Andrew Peterson; Committee Member: Prof. Sungkyu Lim

The objective of this research work is to develop an efficient methodology for chip-package cosimulation. In the traditional design flow, the integrated circuit (IC) is first designed followed by the package design. The disadvantage of the conventional sequential design flow is that if there are problems with signal and power integrity after the integration of the IC and the package, it is expensive and time consuming to go back and change the IC layout for a different input/output (IO) pad assignment. To overcome this limitation, a concurrent design flow, where both the IC and the package are designed together, has been recommended by researchers to obtain a fast design closure. The techniques from this research work will enable multiscale cosimulation of the chip and the package making the concurrent design flow paradigm possible. Traditional time-domain techniques, such as the finite-difference time-domain method, are limited by the Courant condition and are not suitable for chip-package cosimulation. The Courant condition gives an upper bound on the time step that can be used to obtain stable simulation results. The smaller the mesh dimension the smaller is the Courant time step. In the case of chip-package cosimulation the on-chip structures require a fine mesh, which can make the time step prohibitively small. An unconditionally stable scheme using Laguerre polynomials has been recommended for chip-package cosimulation. Prior limitations in this method have been overcome in this research work. The enhanced transient simulation scheme using Laguerre polynomials has been named SLeEC, which stands for simulation using Laguerre equivalent circuit. A full-wave EM simulator has been developed using the SLeEC methodology. A scheme for efficient use of full-wave solver for chip-package cosimulation has been proposed. Simulation of the entire chip-package structure using a full-wave solver could be a memory and time-intensive operation. A more efficient way is to separate the chip-package structure into the chip, the package signal-delivery network, and the package power-delivery network; use a full-wave solver to simulate each of these smaller subblocks and integrate them together in the following step, before a final simulation is done on the integrated network. Examples have been presented that illustrate the technique.