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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Study on no-flow underfill materials for low-cost flip-chip applications

Shi, Songhua 05 1900 (has links)
No description available.
2

Design and implementation of high-Q passive devices for wireless applications using System-On-Package (SOP) based organic technologies

Dalmia, Sidharth 12 1900 (has links)
No description available.
3

Study of warpage of base substrates and materials for large-area MCM-D packaging

Dang, Anh Xuan-Hung 12 1900 (has links)
No description available.
4

Physics-based modeling methodology for reliability of microvias

Ramakrishna, Gnyaneshwar 08 1900 (has links)
No description available.
5

Flip chip assembly process development, process characterization, and reliability assessment of polymer stud grid array-chip scaled package

Paydenkar, Chetan S. 05 1900 (has links)
No description available.
6

Flip chip processing of lead-free solders and halogen-free high density microvia substrates

Baynham, Grant Andrew 05 1900 (has links)
No description available.
7

In-process stress analysis of flip chip assembly and reliability assessment during environmental and power cycling tests

Zhang, Jian 01 December 2003 (has links)
No description available.
8

Study on metal adhesion mechanisms in high density interconnect printed circuit boards

Martin, Lara J. 05 1900 (has links)
No description available.
9

Polymer-Based Wafer-Level Packaging of Micromachined HARPSS Devices

Monadgemi, Pezhman 18 May 2006 (has links)
This thesis reports on a new low-cost wafer-level packaging technology for microelectromechanical systems (MEMS). The MEMS process is based on a revised version of High Aspect Ratio Polysilicon and Single Crystal Silicon (HARPSS) technology. The packaging technique is based on thermal decomposition of a sacrificial polymer through a polymer overcoat followed by metal coating to create resizable MEMS packages. The sacrificial polymer is created on top of the active component including beams, seismic mass, and electrodes by photodefining, dispensing, etching, or molding. The low loss polymer overcoat is patterned by photodefinition to provide access to the bond pads. The sacrificial polymer decomposes at temperatures around 200-280aC and the volatile products permeate through the overcoat polymer leaving an embedded air-cavity. For MEMS devices that do not need hermetic packaging, the encapsulated device can then be handled and packaged like an integrated circuit. For devices that are sensitive to humidity or need vacuum environment, hermiticity is obtained by deposition and patterning thin-film metals such as aluminum, chromium, copper, or gold. To demonstrate the potential of this technology, different types of capacitive MEMS devices have been designed, fabricated, packaged, and characterized. These includes beam resonators, RF tunable capacitors, accelerometers, and gyroscopes. The MEMS design includes mechanical, thermal, and electromagnetic analysis. The device performance, before and after packaging is compared and the correlation to the model is presented. The following is a summary of the main contributions of this work to the extensive research focused on MEMS and their packaging: 1)A new low-cost wafer-level packaging method for bulk or surface micromachined devices including resonators, RF passives and mechanical sensors is reported. This technique utilizes thermal decomposition of a sacrificial polymer through an overcoat polymer to create buried channels on top of the resonant/movable parts of the micromachined device. It provides small interconnections together with resizable package dimensions. We report MEMS package thicknesses in the range of 10 mm to 1 mm, and package size from 0.0001 mm to 1 mm. 2)A revised version of the HARPSS technology is presented to implement high aspect ratio silicon capacitors, resonators and inertial sensors in the smallest area.
10

Modeling and simulation of embedded passives using rational functions in multi-layered substrates

Choi, Kwang Lim 08 1900 (has links)
No description available.

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