In this thesis, a MP3 audio decoder has been designed as System-on-a-Chip using hardware/software co-design techniques. The MP3 audio decoder was built on a fast prototyping platform as ARM Integrator. The hardware architecture was built on the LEON2 SoC architecture, which contained an open source SPARC-V8 architecture compatible processor and an AMBA bus. Because MP3 decoding process was very computation-intensive for software-only decoder to decode in real-time on the LEON2 architecture, an IMDCT and poly phase synthesis filter bank hardware combined core pre-designed as an AMBA compatible core from our lab was reused and integrated. Besides integrating the IP, the MP3 decoding process was changed to use integer calculations instead of floating-point ones. In order to fast prototype LEON2 successfully on ARM Integrator, some modification of the LEON2 SoC hardware architecture was also made for example adding FIFO, modifying the memory controller, etc.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0802105-015335 |
| Date | 02 August 2005 |
| Creators | Teng, Ju-Kai |
| Contributors | Shiann-Rong Kuang, Jer-Min Jou, Pei-Yin Chen, Shen-Fu Siao, Yun-Nan Chang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802105-015335 |
| Rights | restricted, Copyright information available at source archive |
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