Verifying that a hardware module connected to a bus follows the bus protocol correctly is a necessity in a bus-based System-on-Chip (SoC) development. Traditional simulation-based bus protocol monitors can check whether bus signals obey bus protocol or not, but they are non-synthesizable and thus could not identify bugs occurring at run time in real physical environment. We propose a rule-based and synthesizable protocol checker (HPChecker) for AMBA AHB Bus. It contains 73 related bus protocol rules to check bus signal behavior, and two corresponding debugging mechanisms to shorten debugging time. Error reference table can summarize the violation condition of a design under test (DUT); History Memory contains the content of violation signals. These two mechanisms can help designer debugging efficiently. The gate counts of the HPChecker are 43,432 gates and the speed of it is 203 MHz at 0.18Mm technology. Finally, the HPChecker has been integrated into a 3D graphics accelerator and successfully identifies protocol violation in the FPGA prototype. . HPChecker has been successfully licensed to industries in France and Taiwan to assist SoC development.

In current chip multi-processors (CMPs), the on-chip network is a major factor affecting overall system performance. Different kinds of communication protocols vary from different communication architectures of current SOC designs. For example, the AMBA is master-slave architecture, which transacts and communicates the data of between the two CORE (Master) through the Memory (Slave). The architecture cost long time for load and store with memory. Hence, this paper design and implement a Rendezvous protocol on AMBA architecture, which is called Rendezvous of Advanced High performance Bus (RAHB), to let two processors can communicate with each other without memory reference overheads. The RAHB is compatible with the AHB architecture, and add Rendezvous communication protocol in the AMBA architecture to perform the direct transmission of data. Without referring the memory, the RAHB can improve the efficiency of communication in multi-core. For experimental evaluation, we evaluate the performance between RAHB and AHB, RAHB speedup (B/s) is average up to 50% for different data length and performance up 30% to 40% for executing test program.

A computação reconfigurável está se fortalecendo cada vez mais devido ao grande avanço dos dispositivos reprogramáveis e ferramentas de projeto de hardware utilizadas atualmente. Isso possibilita que o desenvolvimento de hardware torne-se bem menos trabalhoso e complicado, facilitando assim a vida do desenvolvedor. A tecnologia utilizada atualmente em projetos de computação reconfigurável é denominada FPGA (Field Programmable Gate Array), que une algumas características tanto de software (flexibilidade), como de hardware (desempenho). Isso fornece um ambiente bastante propício para desenvolvimento de aplicações que precisam de um bom desempenho, sem que estas devam possuir uma configuração definitiva. O objetivo deste trabalho foi implementar um barramento eficiente para possibilitar a comunicação entre diferentes CORES de um robô reconfigurável, que podem estar dispersos em diferentes dispositivos FPGAs. Tal barramento seguirá o padrão AMBA (Advanced Microcontroller Bus Architecture), pertencente à ARM. Todo o desenvolvimento do core completo do AMBA foi realizado utilizando-se a linguagem VHDL (Very High Speed Integrated Circuit Hardware Description Language) e ferramentas EDAs (Electronic Design Automation) apropriadas. É importante notar que, embora o barramento tenha sido projetado para ser utilizado em um robô, o mesmo pode ser usado em qualquer sistema on-chip. / The reconfigurable computing is each time more fortified, what leads to a great advance of reprogrammable devices and hardware design tools. This has become hardware development less laborious and complicated, thus, facilitating the life of the designer. The technology currently used in projects of reconfigurable computing is called FPGA (Field Programmable Gate Array), which combines some characteristics of software (flexibility) and hardware (performance). This technology provides a propitious environment to the development of applications that need a good performance. Those that don’t need a definitive configuration. The purpose of this work was to implement an efficient bus to make possible the communication among different modules of a reconfigurable robot. This bus is based on a bus standard called AMBA (Advanced Microcontroller Bus Architecture), which belongs to ARM. All the development of full AMBA core was carried through using VHDL (Very High Speed Integrated Circuit the Hardware Description Language) language and appropriated EDA (Electronic Design Automation) tools. It is important to notice that, even so the bus have been projected to be used in a robot, it could be used in any system on-chip.

A computação reconfigurável está se fortalecendo cada vez mais devido ao grande avanço dos dispositivos reprogramáveis e ferramentas de projeto de hardware utilizadas atualmente. Isso possibilita que o desenvolvimento de hardware torne-se bem menos trabalhoso e complicado, facilitando assim a vida do desenvolvedor. A tecnologia utilizada atualmente em projetos de computação reconfigurável é denominada FPGA (Field Programmable Gate Array), que une algumas características tanto de software (flexibilidade), como de hardware (desempenho). Isso fornece um ambiente bastante propício para desenvolvimento de aplicações que precisam de um bom desempenho, sem que estas devam possuir uma configuração definitiva. O objetivo deste trabalho foi implementar um barramento eficiente para possibilitar a comunicação entre diferentes CORES de um robô reconfigurável, que podem estar dispersos em diferentes dispositivos FPGAs. Tal barramento seguirá o padrão AMBA (Advanced Microcontroller Bus Architecture), pertencente à ARM. Todo o desenvolvimento do core completo do AMBA foi realizado utilizando-se a linguagem VHDL (Very High Speed Integrated Circuit Hardware Description Language) e ferramentas EDAs (Electronic Design Automation) apropriadas. É importante notar que, embora o barramento tenha sido projetado para ser utilizado em um robô, o mesmo pode ser usado em qualquer sistema on-chip. / The reconfigurable computing is each time more fortified, what leads to a great advance of reprogrammable devices and hardware design tools. This has become hardware development less laborious and complicated, thus, facilitating the life of the designer. The technology currently used in projects of reconfigurable computing is called FPGA (Field Programmable Gate Array), which combines some characteristics of software (flexibility) and hardware (performance). This technology provides a propitious environment to the development of applications that need a good performance. Those that don’t need a definitive configuration. The purpose of this work was to implement an efficient bus to make possible the communication among different modules of a reconfigurable robot. This bus is based on a bus standard called AMBA (Advanced Microcontroller Bus Architecture), which belongs to ARM. All the development of full AMBA core was carried through using VHDL (Very High Speed Integrated Circuit the Hardware Description Language) language and appropriated EDA (Electronic Design Automation) tools. It is important to notice that, even so the bus have been projected to be used in a robot, it could be used in any system on-chip.

In this thesis, a MP3 audio decoder has been designed as System-on-a-Chip using hardware/software co-design techniques. The MP3 audio decoder was built on a fast prototyping platform as ARM Integrator. The hardware architecture was built on the LEON2 SoC architecture, which contained an open source SPARC-V8 architecture compatible processor and an AMBA bus. Because MP3 decoding process was very computation-intensive for software-only decoder to decode in real-time on the LEON2 architecture, an IMDCT and poly phase synthesis filter bank hardware combined core pre-designed as an AMBA compatible core from our lab was reused and integrated. Besides integrating the IP, the MP3 decoding process was changed to use integer calculations instead of floating-point ones. In order to fast prototype LEON2 successfully on ARM Integrator, some modification of the LEON2 SoC hardware architecture was also made for example adding FIFO, modifying the memory controller, etc.

Dissertation--Theologie--Berlin--Humboldt-Universität, 2005. / Bibliogr. f. 185-193.

Diss.--New Heaven, Conn.--Yale university. / Bibliogr. p. 237-244. Index.

The commitment required of a university or business school to gain international accreditation is significant, both in dollar terms and staff time. This thesis seeks to explain the motivations for business schools to seek accreditation with three major accrediting bodies, AACSB International, EFMD and AMBA, using a multiple-case study methodology underpinned by the frameworks of institutional isomorphism, bandwagon pressures and information asymmetry. Interviews were carried out with 17 business school deans; five deans of accredited schools in Europe, five deans of accredited schools in the United States of America and seven business school deans in New Zealand. All the New Zealand schools were either accredited, formally in the process of seeking accreditation or about to enter the application stage. The results provide supporting evidence for the notion that business schools are seeking accreditation in order to achieve legitimacy benefits rather than performance benefits, and that intangible benefits are seen as having more importance than the costs involved with achieving accreditation. It was also found that where the focus is at an international level, accreditation is found to be underpinned by information asymmetries whereby schools are seeking to gain legitimacy by providing signals to the market regarding their quality. At a regional or national level information regarding quality is more well known and, instead, isomorphic and bandwagon pressures become evident as the pathway towards legitimacy. This study will be of value to business school deans in understanding the forces they are being subjected to when considering the value of seeking international accreditation. The results provide an understanding of why, in the absence of a formal business case, a school may consider such a move, or may have entered the process without the hard data that identifies the costs and estimates the benefits in a measurable way. In this regard it will also be of value to all staff of business schools, and of the wider organisation, to understand the phenomenon that is accreditation.

A DMA Controller can offload a processor tremendously. A memory copy operation can be initiated by the processor and while the processor executes others tasks the memory copy can be fulfilled by the DMA Controller. An implementation of a DMA Controller for use in LEON3 SoC:s has been made during this master thesis. Problems that occurred while designing a controller of this type concerned AMBA buses, data transfers, alignment and interrupt handling. The DMA Controller supports AMBA and is attached to an AHB master and APB slave. The DMA Controller supports burst transfers to maximize data bandwidth. The source and destination address can be arbitrarily aligned. It supports multiple channels and it has interrupt generation on transfer completion along with interrupt masking. The implemented functionality works as intended.

Latest trend in multi core architectures is to integrate heterogeneouscores on a single chip in order to achieve task and threadlevel parallelism, high performance and energy efficiency. Someexamples of heterogeneous multi cores processors include (Tegraby NVIDIA,Cell by IBM and Fusion by AMD). The goal of this thesis work is to design a heterogeneous (2x2)network on chip which can run different tasks in parallel on allthe four cores in the network. Development steps of heterogeneousnetwork on chip include integration of Leon3 -a soft core processorby AeroFlex Gaisler which conforms with IEEE 1754 (SPARCV8) architecture- at one of the nodes of a homogeneous networkon chip incorporating four NiosII/s cores -soft core processor byAltera.This integration involves replacing a NiosII/s processor fromone of the four nodes of the homogeneous network by Leon3 processor.To translate the signals between the resource to networkinterface of the node and the Leon3 processor an AMBA bus1 toAvalon bus2 signal translation wrapper was designed. All processorsin the network on chip communicate by message passing interface.To exploit the potential of heterogeneous network on chipthree applications including sparse LU factorization, nqueens andFibonacci numbers calculation were run on it. These applicationwere run on Leon3 SPARC which generated a number of tasks thatcan run in parallel on all cores of the network simultaneously. Thisparallel execution of nqueens and fibonacci numbers calculationhas resulted in speed up as compared to the serial execution ofthese applications on Leon3 SPARC only. Because of the limitedsize of the on chip memory available for the Leon3 processor, itwas not possible to run sparse LU factorization for bigger matrixsizes and this constraint has resulted in no speed up in case ofsparse LU factorization.