Verifying that a hardware module connected to a bus follows the bus protocol correctly is a necessity in a bus-based System-on-Chip (SoC) development. Traditional simulation-based bus protocol monitors can check whether bus signals obey bus protocol or not, but they are non-synthesizable and thus could not identify bugs occurring at run time in real physical environment. We propose a rule-based and synthesizable protocol checker (HPChecker) for AMBA AHB Bus. It contains 73 related bus protocol rules to check bus signal behavior, and two corresponding debugging mechanisms to shorten debugging time. Error reference table can summarize the violation condition of a design under test (DUT); History Memory contains the content of violation signals. These two mechanisms can help designer debugging efficiently. The gate counts of the HPChecker are 43,432 gates and the speed of it is 203 MHz at 0.18Mm technology. Finally, the HPChecker has been integrated into a 3D graphics accelerator and successfully identifies protocol violation in the FPGA prototype. . HPChecker has been successfully licensed to industries in France and Taiwan to assist SoC development.

A DMA Controller can offload a processor tremendously. A memory copy operation can be initiated by the processor and while the processor executes others tasks the memory copy can be fulfilled by the DMA Controller. An implementation of a DMA Controller for use in LEON3 SoC:s has been made during this master thesis. Problems that occurred while designing a controller of this type concerned AMBA buses, data transfers, alignment and interrupt handling. The DMA Controller supports AMBA and is attached to an AHB master and APB slave. The DMA Controller supports burst transfers to maximize data bandwidth. The source and destination address can be arbitrarily aligned. It supports multiple channels and it has interrupt generation on transfer completion along with interrupt masking. The implemented functionality works as intended.

This master thesis deals with the design of a RISC-V processor with bit manipulations instruction set extension. In this work, attention is paid to the description of the RISC-V instruction set and the CodAL language, which is used to describe the instruction sets and the processor architectures. The main goal of this work is to implement a model with a 32-bit address space, RISC-V basic instruction set and bit manipulations instruction set. The processor's design have two models, which one is instruction model and second is RTL model. The resulting parameters of the designed processor are measured using a Genus Synthesis Solution tool. The usability of bit manipulations based on decoder coverage is also included in the measurement.

Asynchronous bus interface units to AMBA AHB are designed so that an OpenGL ES 2.0 vertex shader can communicate with other hardware units via AHB bus under different working frequencies. The first design is to directly implement an asynchronous AHB wrapper for the vertex shader. The other two designs are based on Open Core Protocol (OCP) to allow for more flexibility. The hardware intellectual property (IP), vertex shader in this thesis, to OCP asynchronous unit is designed so that the IP can be developed independently with different bus protocols as long as the OCP-to-bus interface is provided for a particular bus protocol. With the help of asynchronous IP-to-OCP and OCP-to-AHB interface units, the vertex shader IP can operate at different frequencies from the AHB bus. Furthermore, the same vertex shader (VS) can be connected to other bus protocol (such as AXI) of different frequencies if the OCP-to-AXI interface is provided because the the asynchronous VS-to-OCP have been designed in this thesis.

Η παρούσα διπλωματική αποτελεί την προσπάθεια κατασκευής ενός cache controller βασισμένο στον AHB BUS. Η ανάπτυξή του έγινε ως επί το πλείστο στο Εργαστήριο Vlsi του τμήματος Μηχανικών Υπολογιστών και Πληροφορικής με την προοπτική να ενσωματωθεί σε ένα ευρύτερο υπάρχων σύστημα βασισμένο στον open source cpu της arm Cortex M0. Δοκιμάστηκε επιτυχώς σε FPGA του εργαστηρίου αλλά ακόμα δεν έχει χρησιμοποιηθεί σε «πραγματικές συνθήκες». Απώτερος στόχος είναι να χρησιμοποιηθεί στο εργαστήριο για την επιτάχυνση εφαρμογών που θα χρειαστούν εξωτερική μνήμη δηλ. μεγαλύτερη μνήμη από την embedded του FPGA. Αν και δεν δοκιμάστηκε σε κάποιο άλλο σύστημα έχει φτιαχτεί με γνώμονα το πρότυπο του AHB οπότε υποθετικά δεν θα έχει κάποιο πρόβλημα να ενσωματωθεί σε οποιοδήποτε συμβατό με τον δίαυλο σύστημα. Η λογική πίσω από την υλοποίηση του είναι να είναι σχετικά εύκολη η αλλαγή ορισμένων μεταβλητών ώστε να διαφοροποιείται ο controller βάση των αναγκών του καθενός. Οι προδιαγραφές δίνονται παρακάτω αν και πιθανόν εκτός των πλαισίων της διπλωματικής και εντός του 2014 να επανα-σχεδιαστεί ώστε να γίνει πλήρως modular. / Cache controller compatible with AHB bus in system Verilog.

In this work was studying literature related to object orientated programming tools for hardware design, capabilities for modeling and synthesis of high-level models of abstraction. It was founded-out the operating principles of high-speed bus and created prototype of such bus in TLM level. It was created methodology for transformation of high-speed bus prototype to RTL level. This methodology was used for transformation of high-speed bus prototype to RTL level. Transformed module was synthesized to gate level. Simulation speed of high-speed bus model in TLM was compared with simulation speed of model in behavioral level. It was demonstrated universality and reuse capabilities of TLM models.

Africanized honey bees (AHB) are a hybrid between African and European honey bees (EHB). Compared to the EHB, AHB exhibit more intense, defensive behaviors but nevertheless provide the same important ecosystem service--pollination. AHB have been found in Tucson, AZ. since 1993. It is important to understand the population ecology of AHB for several reasons. Most directly, the behavioral traits retained from African bees present public safety and health risk. AHB are easily agitated; even slight disturbances (e.g., human movements) can provoke attacks. Several hybridized bee traits (e.g., higher colony growth rates, reproduction at a smaller colony size, nesting in a wider range of cavity materials, etc.) also make them more adapted to urban landscapes. The overlap of habitats and resource-using of AHB with human significantly raise the risk of stinging incidents, especially in the areas of bee aggregation. Although the presence of AHB in urban environments may present a public safety and health risk, they do contribute to urban ecosystems substantially through pollination. The fact that AHB is a part of the urban ecosystem suggests a need for a better understanding of the relationship among climate factors, urban landscape characteristics, and AHB population dynamics. The goal of my dissertation was to understand population dynamics of AHB in urban environments using removal records of AHB colonies in water meter boxes. I have demonstrated useful methods and repeatable procedures to process, extract, and synthesize water meter box data which were not collected or sampled specifically for any ecological research. I also examined the spatio-temporal distributions of AHB colony removals in water meter boxes, and evaluated the effects of variations of temperature and precipitation on observed patterns. Then, I investigated the linkage between spatial patterns of AHB colonies and urban landscape characteristics by evaluating densities of water meter boxes, AHB colony abundance, and colony occupancy among different land cover/land use types. Lastly, a conceptual model and quantitative models were developed to illustrate AHB population dynamics, particularly and the interactions among water meter boxes, alternative cavities, and honey bee colonies. Overall, the probabilities of AHB colonies selecting nesting sites can be influenced by: (1) the ratio of water meter boxes and alternative cavities; (2) the difference of vegetative attributes among locations associated with the preference of AHB in selecting new nesting sites. Seasonal variations of precipitation and temperature can affect the development and productivity of AHB population.

The thesis deals with design and implementation of controllers for the RMAP protocol, which is used by SpaceWire network endpoints to access memory contents of another endpoint. The theoretical research introduces concepts of the SpaceWire network, then describes the RMAP protocol and the AMBA AHB bus interface in detail. The practical part of this thesis then uses this information to design and implement controllers for the RMAP protocol. It first defines an architecture of these controllers, then describes design of individual blocks based on this architecture. As a next step, the thesis describes methods used to verify designed controllers and to test these controllers in an FPGA chip. Finally, an analysis of maximum frequency and usage of FPGA resources is done based on estimates provided by the synthesis tool.

Aufgrund der wachsenden Ressourcen heutiger FPGAs, durch neue technologische Entwicklungen, erschließen sich immer neue Einsatzmöglichkeiten.Beispielsweise wächst der Wunsch, ein vollständiges System in einem einzigen Chip einzubringen. Die sogenannten Systems-on-Chip (kurz SoC) bestehen dabei aus einem Prozessor, einen Bussystem, Schnittstellen zu externen Speichern und anderen Peripheriegeräten. Die Firma Xilinx bietet mit ihrer Software EDK eine IP-Core Bibliothek an, mit der es möglich ist, ein komplettes SoC für einen FPGA zu synthetisieren. Die Xilinx-IP-Core-Bibliothek benutzt dabei den Soft-Prozessor MicroBlaze als μP. Die IP-Core Bibliothek von Xilinx ist nicht Open-Source und zu ihrer Benutzung werden Lizenzgebühren verlangt. In dieser Arbeit wird eine neue IP-Core Bibliothek bereitgestellt, welche Open-Source ist und damit frei einsehbar und frei verwendbar ist. Die neue IP-Core Bibliothek wird durch diese Arbeit in den Workflow des Xilinx-EDK eingebunden und ist somit komfortabel benutzbar. Als Grundlage dient die IP-Core Bibliothek der Firma Gaisler Research, auch genannt Gaisler Research Library (kurz GRLIB). Die GRLIB besitzt eine Vielzahl von IP-Cores unter denen, für jeden IP-Core der Xilinx Bibliothek, ein Ersatz gefunden werden konnte. Die GRLIB setzt als μP auf den LEON3-Prozessor. Der LEON3-Prozessor wurde nach den Spezifikationen der SPARC entworfen und ist ein höchst flexibler und konfigurierbarer Soft-Prozessor. In dieser Arbeit wurde weiterhin das SnapGear-Linux evaluiert, welches auf dem LEON3- Prozessor mit Komponenten der GRLIB ausgeführt werden kann.

En este trabajo se presenta el estudio de arquitecturas de bus y la implementaci on de AMBA AHB-Lite en el marco de un sistema que incluye un microprocesador basado en la arquitectura MIPS32, cuya interfaz es adaptada para ser compatible con las especi caciones del protocolo mencionado. Se realiza una comparaci on del sistema implementado con respecto a otras arquitecturas est andar que emplean procesadores como Cortex-M0, OpenRISC1200, ZPU y LEON3, contrastando los requisitos que cada uno insume en sus implementaciones en FPGA y el desempe~no alcanzado por cada uno. / This work presents the study of bus architectures and the implementation of AMBA AHB-Lite in the context of a system that includes a microprocessor based on the MIPS32 architecture, whose interface is modi ed to comply with the protocol's speci cations. The implemented system is compared with other standard architectures that employ microprocessors such as Cortex-M0, OpenRISC1200, ZPU y LEON3, examining the requirements needed for each case in their FPGA implementation and the performance yielded by each of them.