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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Sparčiosios magistralės aukšto abstrakcijos lygio modelio sudarymas ir analizė / Analysis and creation of high-speed bus model in high level of abstraction

Pečkys, Vaidotas 26 May 2005 (has links)
In this work was studying literature related to object orientated programming tools for hardware design, capabilities for modeling and synthesis of high-level models of abstraction. It was founded-out the operating principles of high-speed bus and created prototype of such bus in TLM level. It was created methodology for transformation of high-speed bus prototype to RTL level. This methodology was used for transformation of high-speed bus prototype to RTL level. Transformed module was synthesized to gate level. Simulation speed of high-speed bus model in TLM was compared with simulation speed of model in behavioral level. It was demonstrated universality and reuse capabilities of TLM models.
2

UML aprašų transformacijos į srities kalbą (VHDL,SystemC) / Transformation of UML notations to domain language (VHDL,SystemC)

Aklys, Andrius 05 June 2006 (has links)
To increase the productivity of electronic systems design we offer to use UML – the standard specification language of high level systems. The higher level of abstraction and automatic design methods could decrease a gap of hardware design. We offer to use UML class diagrams for the specification of electronic systems structure and UML state diagrams to specify the behavior of electronic systems. We introduce metamodels which describe mapping between UML class and state diagrams and hardware description languages (VHDL, SystemC), as the possible realization of ideas we introduced earlier. Also we provide code generator which translates notations of UML class and state diagrams to VHDL and SystemC languages.

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