Recent interest in approximate computation is driven by its potential to achieve large energy savings. We formally demonstrate an optimal way
to reduce energy via voltage over-scaling at the cost of errors due to timing starvation in addition. A fundamental trade-off between error frequency and error magnitude in a timing-starved adder has been identified. We introduce a formal model to prove that for signal processing applications using a quadratic signal-to-noise ratio error measure, reducing bit-wise error frequency
is sub-optimal. Instead, energy-optimal approximate addition requires limiting maximum error magnitude. Intriguingly, due to possible error patterns,
this is achieved by reducing carry chains significantly below what is allowed by the timing budget for a large fraction of sum bits, using an aligned, fixed internal-carry structure for higher significance bits.
We further demonstrate that remaining approximation error is reduced by realization of conditional bounding (CB) logic for lower significance bits.
A key contribution is the formalization of an approximate CB logic synthesis problem that produces a rich space of Pareto-optimal adders with a range of quality-energy trade-offs. We show how CB logic can be customized to
result in over- and under-estimating approximate adders, and how a dithering adder that mixes them produces zero-centered error distributions, and, in
accumulation, a reduced-variance error. This work demonstrates synthesized
approximate adders with energy up to 60% smaller than that of a conventional timing-starved adder, where a 30% reduction is due to the superior
synthesis of inexact CB logic. When used in a larger system implementing an
image-processing algorithm, energy savings of 40% are possible. / text
| Identifer | oai:union.ndltd.org:UTEXAS/oai:repositories.lib.utexas.edu:2152/19706 |
| Date | 04 March 2013 |
| Creators | Miao, Jin |
| Source Sets | University of Texas |
| Language | en_US |
| Detected Language | English |
| Format | application/pdf |
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