PIM ¡]Processor-in-Memory¡^ architectures have been proposed in recent years for the purpose of reducing performance gap between processor and memory. This new class of computer architectures attempts to integrate processor and memory on a single one chip¡CWe proposed a new transformation and parallelizing system named SAGE ¡]Statement Analysis Group Evaluation¡^to fully utilize the host processor and memory processors in PIM systems. In this thesis, we focus on designing a load-balance optimization mechanism for the job scheduling. The experimental results of this mechanism are also discussed.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0826102-154856 |
| Date | 26 August 2002 |
| Creators | Huang, Jyh-Chiang |
| Contributors | Chih-Ping Chu, Chyi-Ren Dow, Tsung-Chuan Huang, Ting-Wei Hou |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0826102-154856 |
| Rights | unrestricted, Copyright information available at source archive |
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