In recent years, many researchers had proposed a new class of computer architecture, called processor-in-memory (PIM), to reduce the performance gap between the CPU and memory. In order to exploit the benefits of PIM, we designed a parallelizing system ¡V SAGE (Statement Analysis Grouping Evaluation) in our previous research. In this paper, we design a program decomposition mechanism for SAGE system. The mechanism partitions the statements in a program into several parts according to control flow relation. Then it analyzes data dependence relation by using Polaris system, and generates weighted partition dependence graphs which are scheduled by task scheduling mechanisms of SAGE system.

In order to reduce the performance gap between the processor and the memory subsystem, many researchers attempt to integrate the processor and memory on a single chip in recent years. Therefore a new class of computer architecture: PIM (Processor-in-Memory) are investigated. For this class of architecture, we propose a new transformation and parallelizing system, SAGE, to achieve the benefits of PIM architectures by fully utilizing the capabilities of the host processor and memory processors in the PIM system. In this thesis, we focus on the weight evaluation mechanism and 1H-nM scheduling mechanism. The weight evaluation mechanism is used to evaluate the weights of P.Host and P.Mem for each task. The 1H-nM scheduling mechanism takes two different weights into account to exploit the advantages of two kinds of processors in the PIM system. The experimental results of above mechanisms are also discussed.

PIM ¡]Processor-in-Memory¡^ architectures have been proposed in recent years for the purpose of reducing performance gap between processor and memory. This new class of computer architectures attempts to integrate processor and memory on a single one chip¡CWe proposed a new transformation and parallelizing system named SAGE ¡]Statement Analysis Group Evaluation¡^to fully utilize the host processor and memory processors in PIM systems. In this thesis, we focus on designing a load-balance optimization mechanism for the job scheduling. The experimental results of this mechanism are also discussed.

Power consumption is gradually becoming an important issue in designing computing systems. Most of the low power researches focused on semiconductor technique and hardware architecture design but less utilized the techniques of software optimization. In this thesis, list scheduling is employed to reduce the energy cost for the Processor-in-Memory system not at the sacrifice of execution performance. In our list-based low power scheduling algorithm, a priority list will be maintained for each scheduling step. The scheduling kernel utilizes the priority of mobility to determine which task will be scheduled to the suitable processor based on the energy cost model of energy-delay product. The experimental results are presented and discussed.

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Continuous improvements in semiconductor fabrication density are enabling new classes of System-on-a-Chip (SoC) architectures that combine extensive processing logic/processing with high-density memory. Such architectures are generally called Processor-in-Memory or Intelligent Memory and can support high-performance computing by reducing the performance gap between the processor and the memory. This architecture combines various processors in a single system. These processors are characterized by their computational and memory-access capabilities in performance and energy consumption. Two main problems addressed here are how to improve the performance and reduce the energy consumption of applications running on Processor-in-Memory architectures. Accordingly, a novel strategy must be developed to identify the capabilities of the different processors and dispatch the most appropriate jobs to them to exploit them fully. Accordingly, this study proposes a novel automatic source-to-source parallelizing system, called SAGE, to exploit the advantages of Processor-in-Memory architectures. Unlike conventional iteration-based parallelizing systems, SAGE adopts statement-based analytical approaches. The strategy of the SAGE system, which decomposes the original program into blocks and produces a feasible execution schedule for the host and memory processors, is also investigated. Hence, several techniques including statement splitting, weight evaluation, performance scheduling and energy reduction scheduling are designed and integrated into the SAGE system to automatically transform Fortran source programs to improve the performance of the program or reduce energy consumed by the program executed on Processor-in-Memory architecture. This thesis provides detailed techniques and discusses the experimental results of real benchmarks which are transformed by SAGE system and targeted on the Processor-in-Memory architecture.