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The Design of an Effective Load-Balance Mechanism for Processor-in-Memory Systems

PIM ¡]Processor-in-Memory¡^ architectures have been proposed in recent years for the purpose of reducing performance gap between processor and memory. This new class of computer architectures attempts to integrate processor and memory on a single one chip¡CWe proposed a new transformation and parallelizing system named SAGE ¡]Statement Analysis Group Evaluation¡^to fully utilize the host processor and memory processors in PIM systems. In this thesis, we focus on designing a load-balance optimization mechanism for the job scheduling. The experimental results of this mechanism are also discussed.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0826102-154856
Date26 August 2002
CreatorsHuang, Jyh-Chiang
ContributorsChih-Ping Chu, Chyi-Ren Dow, Tsung-Chuan Huang, Ting-Wei Hou
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageCholon
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0826102-154856
Rightsunrestricted, Copyright information available at source archive

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